1: The CPU

Question 1

CU

Answer 1

• Coordinates all activities of the CPU
• Directs the flow of data between the CPU and other devices
• FDE cycle happens here
• Sends memory read/write signals to main memory on the control bus

Question 2

PC

Answer 2

• Holds the address of the next instruction to be executed
• Holds a close relationship with MAR: the address held in the PC is copied to the MAR

Question 3

MAR

Answer 3

-Holds the address of the memory location from which data is to be fetched or to which data is to be written
-Sends addressed to memory down address bus

Question 4

MDR

Answer 4

• Temporarily stores the data which has been read from or written to memory
• All data to and from memory must pass through the MDR via the data bus.

Question 5

CIR

Answer 5

• Holds the current instruction being executed
• Contents of MDR are copied into CIR if it is an instruction
• Contains opcode and operands of the current instruction
• Instruction = opcode + operands

Question 6

ALU

Answer 6

-performs arithmetic and logic functions in the CPU
-ADD, SUBTRACT, MULTIPLY, DIVIDE
- AND, OR, NOT, XOR
- Binary shift
-Comparison

Question 7

ACC

Answer 7

• a general purpose register which stores results of calculations performed in the ALU as well as control information
• The more general purpose registers a CPU has, the faster it may operate

Question 8

Address Bus

Answer 8

Carries memory addresses that identify where the data is being read or written to

Question 9

Data Bus

Answer 9

Carries the binary that make up the actual information being transmitted around the CPU

Question 10

features of Von Neumann architecture

Answer 10

• Shared memory space for instructions and data
• Instructions and data are stored in the same format
• A single control unit or processor follows a linear FDE cycle
• One instruction at a time
• Registers are used as fast access to instructions and data

Question 11

Features of Harvard architecture

Answer 11

• Instructions and data stored in separate memory units
• each has its own bus
• Reading and writing data can be done at the same time as fetching an instruction
• Used by RISC processors

Question 12

How do Von Neumann and Harvard architectures differ from contemporary architectures?

Answer 12

• SIMD (Single Instruction Multiple Data): Parallel processing is where a processor carries out a single instruction on multiple data items at the same time - often used by graphic processors
• MIMD (Multiple Instructions Multiple Data), another version where multiple instructions are carried on multiple data items across several cores
• Distributed computing : Where multiple computers on a shared network each take part on part of a bigger problem

Question 13

Clock Speed

Answer 13

• measured in hertz (Hz)
• Number of FDE cycles per second

Question 14

Cache size

Answer 14

• Temporary storage of frequently used data and instructions being read to and written from
• Located on or near the CPU
• Stores copies of recent data and instructions
• Quicker to access than RAM, improving efficiency of CPU

Question 15

Number of cores

Answer 15

• A core is a complete copy of the CPU, with its own separate registers and units
• CPUs with multiple cores have more power to run multiple programs at the same time

Question 16

What are registers?

Answer 16

Small memory cells that operate at very high speeds and used to temporarily store data involved in the FDE cycle.

Question 17

Fetch

Answer 17

• Address from the PC is copied to the MAR
• Instructions held at that address is copied to the MDR by the data bus
• simultaneously the PC is incremented
• The value held in the MDR is copied to the CIR

Question 18

Decode

Answer 18

• The contents of CIR are split into opcode and operand

Question 19

Execute

Answer 19

-The opcode is executed on the operand.

Question 20

ADD

Answer 20

add

Question 21

SUB

Answer 21

subtract

Question 22

STA

Answer 22

store

Question 23

LDA

Answer 23

load

Question 24

BRA

Answer 24

Branch Always

Question 25

BRZ

Answer 25

Branch if zero

Question 26

BRP

Answer 26

Branch if positive

Question 27

INP

Answer 27

input

Question 28

OUT

Answer 28

output

Question 29

Control Bus

Answer 29

Carries command and control signals to and from every other component of the CPU/computer

Question 30

HLT

Answer 30

End program

Question 31

DAT

Answer 31

Data Location

Question 32

What is pipelining?

Answer 32

- The process of completing the fetch, decode and execute cycles of three separate instructions simultaneously - the appropriate data is held in a buffer in close proximity to the CPU until it is required - while one instruction is being executed, another can be decoded and another fetched

Question 33

What is the aim of pipelining?

Answer 33

To reduce the amount of the CPU kept idle

Question 34

What does instruction pipelining do?

Answer 34

Separate the instruction into fetching, decoding and executing

Question 35

What does arithmetic pipelining do?

Answer 35

Break down the arithmetic operations and overlapping them as they are performed