1.4 Data types, data structures and algorithms Flashcards

(27 cards)

1
Q

Sign and magnitude

A

First bit = sign (0 = +, 1 = -); remaining bits = magnitude. Issue: two zeros (+0/-0).

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2
Q

Two’s complement

A

Negative numbers: invert bits + add 1. Solves negative zero; simplifies subtraction.

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3
Q

Normalisation (floating point)

A

Adjusts mantissa/exponent so mantissa starts with 0.1 (positive) or 1.0 (negative); maximises precision.

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4
Q

Renormalisation after arithmetic

A

After addition/subtraction, mantissa may need shifting left/right and exponent adjusting to maintain normalised form.

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5
Q

Bitwise AND mask use

A

Used to clear bits (set to 0).

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6
Q

Bitwise OR mask use

A

Used to set bits (set to 1).

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7
Q

XOR bitwise use

A

Used to toggle/flip bits.

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8
Q

Difference between ASCII and UNICODE

A

ASCII = 7/8 bit, 128/256 chars, English focused. UNICODE = 16/32 bit, covers global characters (emojis, symbols).

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9
Q

UTF-8 vs UTF-16

A

UTF-8: Variable length (1-4 bytes), ASCII compatible. UTF-16: 2 or 4 bytes, better for Asian languages.

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10
Q

Stack (LIFO)

A

Last In, First Out. Push, Pop. Uses: call stack, undo function.

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11
Q

Queue (FIFO)

A

First In, First Out. Enqueue, Dequeue. Uses: print spooler, ready queue.

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12
Q

Linked list

A

Nodes containing data and pointer to next node; dynamic size; sequential access.

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13
Q

Binary Search Tree property

A

Left child < Parent < Right child.

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14
Q

Hash table

A

Uses hash function to compute index; O(1) average lookup.

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15
Q

Graph (directed vs undirected)

A

Directed: edges have direction (one-way). Undirected: edges are bidirectional.

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16
Q

Tree

A

Hierarchical structure; root, parent, child, leaf nodes; no cycles.

17
Q

How to delete from a linked list?

A

Adjust pointers of previous node to skip the node to be deleted; deallocate memory.

18
Q

De Morgan’s First Law

A

NOT (A AND B) = (NOT A) OR (NOT B).

19
Q

De Morgan’s Second Law

A

NOT (A OR B) = (NOT A) AND (NOT B).

20
Q

Distribution law

A

A AND (B OR C) = (A AND B) OR (A AND C); A OR (B AND C) = (A OR B) AND (A OR C).

21
Q

Association law

A

(A AND B) AND C = A AND (B AND C); (A OR B) OR C = A OR (B OR C).

22
Q

Commutation law

A

A AND B = B AND A; A OR B = B OR A.

23
Q

Double negation

A

NOT (NOT A) = A.

24
Q

D type flip flop

A

1-bit memory; stores state on clock edge; data (D) transferred to output (Q).

25
Edge-triggered
Flip flop only changes state on rising or falling edge of clock signal.
26
Half adder outputs
Sum = A XOR B; Carry = A AND B.
27
Full adder difference to half adder
Includes a Carry-in (CIN) input to chain multiple bits.