4.1. Central Processing Unit Architecture

Question 1

Von Neumann model

Answer 1

• Von Neumann realized data & programs are
  indistinguishable and can therefore use same
  memory.
• Von Neumann architecture uses a single processor.
• It follows a linear sequence of fetch–decode–execute
  operations for the set of instructions i.e. the program.
  In order to do this, the processor uses registers.

Question 2

Define Registers

Answer 2

Smallest unit of storage of microprocessor;
allows fast data transfer between other registers

Question 3

General Purpose registers

Answer 3

• Used to temporarily store data values which have
  been read from memory or some processed result
• Can be used by assembly language instructions

Question 4

Special Purpose Registers

Answer 4

• Some are accessible by assembly language
  instructions
• Only holds either data or memory location, not both

Question 5

Special purpose registers include

Answer 5

• Program Counter (PC): holds address of next
  instruction to be fetched
• Memory Data Register (MDR): holds data value
  fetched from memory
• Memory Address Register (MAR): Holds address of
  memory cell of program which is to be accessed
• Accumulator (ACC): holds all values that are
  processed by arithmetic & logical operations.
• Index Register (IX): Stores a number used to
  change an address value
• Current Instruction Register (CIR): Once program
  instruction fetched, it is stored in CIR and allows
  the processor to decode & execute it
• Status Register: holds results of comparisons to
  decide later for action, intermediate and
  erroneous results of arithmetic performed

Question 6

The Processor (CPU)

Answer 6

• Arithmetic and Logic Unit (ALU): part of processor that
  processes instructions which require some form of
  arithmetic or logical operation
• Control Unit (CU): part of CPU that fetches
  instructions from memory, decodes them &
  synchronizes operations before sending signals to
  computer’s memory, ALU and I/O devices to direct
  how to respond to instructions sent to processor
• Immediate Access Store (IAS): memory unit that can
  be directly accessed by the processor
• System Clock: timing device connected to processor
  that is needed to synchronize all components.

Question 7

Buses

Answer 7

Set of parallel wires that allow the transfer data
between components in a computer system

Question 8

Data bus

Answer 8

Bidirectional bus that carries data
instructions between processor, memory, and I/O
devices.

Question 9

Address bus

Answer 9

Unidirectional bus that carries
address of main memory location or input/output
device about to be used, from processor to
memory address register (MAR)

Question 10

Control bus

Answer 10

• Bidirectional and unidirectional
• Used to transmit control signals from control unit
  to ensure access/use of data & address buses by
  components of system does not lead to conflict

Question 11

Performance of Computer System Factors

Answer 11

Clock Speed, Bus Width, Cache Memory, Number of Cores

Question 12

Clock Speed

Answer 12

• Number of pulses the clock sends out in a given
  time interval, which determines the number of
  cycles (processes) CPU executes in a given time
  interval
• Usually measured in Gigahertz (GHz)
• If the clock speed is increased, then execution
  time for instructions decreases. Hence, more
  cycles per unit time, which increases performance.
• However, there is a limit on clock speed since the
  heat generated by higher clock speeds cannot be
  removed fast enough, which leads to overheating

Question 13

Bus Width

Answer 13

• Determines number of bits that can be
  simultaneously transferred
• Refers to number of lines in a bus
• Increasing bus width increases number of bits
  transferred at one time, hence increasing
  processing speed and performance since there

Question 14

Cache Memory

Answer 14

• Commonly used instructions are stored in the
  cache memory area of the CPU.
• If cache memory size is increased, more
  commonly executed instructions can be stored
  and the need for the CPU to wait for instructions
  to be loaded reduces, hence CPU executes more
  cycles per unit time, thus improving performance

Question 15

Number of Cores

Answer 15

• Most CPU chips are multi-core — have more than
  one core (essentially a processor)
• Each core simultaneously processes different
  instructions through multithreading, improving
  computer performance

Question 16

Ports

Answer 16

• Hardware which provides a physical interface
  between a device with CPU and a peripheral device
• Peripheral (I/O) devices cannot be directly connected
  to CPU, hence connected through ports
• Universal Serial Bus (USB): Can connect both input
  and output devices to processor through a USB port
• High Definition Multimedia Interface (HDMI)
• Can only connect output devices (e.g. LCD display)
  to the processor through a HDMI port
• HDMI cables transmit high-bandwidth and highresolution video & audio streams through HDMI
  ports

Question 17

Video Graphics Array (VGA)

Answer 17

• Can only connect output devices (e.g. second
  monitor/display) to the processor through a VGA
  port
• VGA ports allows only the transmission of video
  streams, but not audio components

Question 18

Fetch-Execute (F-E) cycle

Answer 18

• Fetch stage
• Decode stage
• Execute stage

Question 19

Fetch stage

Answer 19

• PC holds address of next instruction to be fetched
• Address in PC is copied to MAR
• PC is incremented
• Instruction loaded to MDR from address held in MAR
• Instruction from MDR loaded to CIR

Question 20

Decode stage

Answer 20

• The opcode and operand parts of
  instruction are identified

Question 21

Execute stage

Answer 21

• Instructions executed by the control
  unit sending control signals

Question 22

Register Transfer Notation (RTN)

Answer 22

• MAR ← [PC]
• PC ← [PC] + 1
• MDR ← [[MAR]]
• CIR ← [MDR]
• Decode
• Execute
• Return to start
• Square brackets: value currently in that register
• Double square brackets: CPU is getting value
  stored at the address in the register

Question 23

Interrupts

Answer 23

• A signal from a program seeking processor’s attention
• Interrupt Service Routine (ISR):
• Handles the interrupt by controlling the processor
• Different ISRs used for different sources of
  interrupt

Question 24

Typical sequence of actions when interrupt occurs

Answer 24

• The processor checks interrupt register for interrupt
  at the end of the F-E cycle for the current instruction
• If the interrupt flag is set in the interrupt register, the
  interrupt source is detected
• If interrupt is low priority: then interrupt is disabled
• If interrupt is high priority:
• All contents of registers of the running process are
  saved on the stack
• PC is loaded with the ISR, and is executed
• Once ISR is completed, the processor restores
  registers’ contents from the stack, and the
  interrupted program continues its execution
• Interrupts re-enabled and
• Return to start of cycle