Application Processor Part 1

Question 1

What is the Arithmetic/ Logic Unit?

Answer 1

Operate on values stored in the Registers

Question 2

What is a register?

Answer 2

Group of flip-flops with common clock used to store binary data

Question 3

What is the instruction register?

Answer 3

Hold current instruction.

Question 4

What is the instruction pointer?

Answer 4

Hold the address of the next instruction in memory

Question 5

What is RISC?

Answer 5

Reduced Instruction Set Computer. Only execute one instruction at a time but usually take one machine cycle.

Question 6

What is CISC?

Answer 6

Complex Instruction Set Computer. Executes an instruction over a span of two to ten machine cycles but can execute multiple steps of each instruction at the same time.

Question 7

What is the CORTEX A series used in?

Answer 7

Smartphones, digital TV, servers and networking.

Question 8

What is the CORTEX R series used in?

Answer 8

Automotive Braking systems, powertrain solutions, and mass storage controller.

Question 9

What is the CORTEX M series used in?

Answer 9

Micro controllers, mixed signal devices, and smart sensors

Question 10

What are the main features of ARMv7 A architecture?

Answer 10

• Large uniform register file
• 32 bit processor
• Instructions are 32 bit long
• Good speed/power consumption ratio
• High code density

Question 11

What are the enhancements to basic RISC features?

Answer 11

• Control over ALU and shifter for every data processing operation to maximize there usage.
• Auto-increment and auto-decrement addressing modes to optimize program loops
• Load and store multiple instructions to maximize data throughput
• Conditional execution of instruction to maximize execution throughput.

Question 12

What does the ARM Core Registers do?

Answer 12

• The general purpose registers hold either data or address.
• All registers are 32 bits
• In user mode 16 data registers and 2 states registers are visible

Question 13

What is the function of register r13?

Answer 13

Stack pointer (can also be used as GPR)

Question 14

What is the function of register r14?

Answer 14

Link register (where return address is put whenever a subroutine is called and can be used as GPR)

Question 15

What is the function of register r15?

Answer 15

Program counter

Question 16

What are the two status registers?

Answer 16

• CPSR : current program status register

- SPSR : saved program status register

Question 17

What are the flags of CPSR?

Answer 17

• Condition code flags
• Sticky overflow flag
• J bit
• Interrupt disable bits
• T Bit
• Mode bits

Question 18

What are the flags of condition code flags?

Answer 18

• N : Negative result from ALU
• Z : Zero result from ALU
• C : ALU operation Carried out
• V : ALU operation oVerflowed

Question 19

What does flag N of condition code flags do?

Answer 19

• Logical Instruction : No meaning

- Arithmetic Instruction : Bit 31 of the result has been set. Indicates a negative number in signed operations

Question 20

What does flag Z of condition code flags do?

Answer 20

• Logical Instruction : Results in all zeros

- Arithmetic Instruction : Result of operation was zero

Question 21

What does flag C of condition code flags do?

Answer 21

• Logical Instruction : After Shift operation ‘1’ was left in carry flag
• Arithmetic Instruction : Result was greater than 32 bits

Question 22

What does flag V of condition code flags do?

Answer 22

• Logical Instruction : No meaning
• Arithmetic Instruction : Result was greater than 31 bits. Indicates a possible corruption of the sign bit in signed numbers

Question 23

What does the processor mode determines?

Answer 23

• Which registers are active

- Access rights to CPSR register itself

Question 24

What is privileged and non-privileged?

Answer 24

Privileged : full read-write access to CPSR

Non-privileged : only read access to the control field of CPSR but read-write access to the condition flags.

Question 25

What are the basic operating modes?

Answer 25

- User - FIQ - IRQ - Supervisor - Abort - Undef - System

Question 26

What does User mode do?

Answer 26

Unprivileged mode under most tasks are run

Question 27

What does FIQ mode do?

Answer 27

Entered when a high priority (fast) interrupt is raised

Question 28

What does IRQ mode do?

Answer 28

Entered when a low priority (normal) interrupt is raised

Question 29

What does Supervisor mode do?

Answer 29

Entered on reset

Question 30

What does Abort mode do?

Answer 30

Used to handle memory access violations

Question 31

What does Undef mode do?

Answer 31

Used to handle undefined instructions

Question 32

What does System mode do?

Answer 32

Privileged mode using the same registers as user mode

Question 33

What is Banked Registers?

Answer 33

- 20 registers are hidden from program at different times - Available in certain modes - Maps one-to-one onto a user mode register

Question 34

What is the saved program status register (SPSR)?

Answer 34

- SPSR is associated with privileged mode except system mode | - Used to save the state of CPSR when the privileged mode is entered

Question 35

What is mode changing?

Answer 35

- By writing directly to CPSR or by hardware when the processor responds to exception or interrupt - To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers

Question 36

What is included in the ARM instructions set?

Answer 36

- Data processing instructions - Data transfer instructions - Block transfer instructions - Branching instructions - Multiply instructions - Software interrupt instructions

Question 37

What is data processing?

Answer 37

``` Manipulate data - MOVE instructions - Arithmetic instructions - Logical instructions - Comparison instructions Suffix S on data processing instructions updates flags in CPSR ```

Question 38

How does data processing instructions work?

Answer 38

- Operands are 32 bit wide; come from registers or specified as literals in the instruction itself - Second operand sent to ALU via barrel shifter - 32 bit result placed in register; long multiply instruction produces 64 bit result

Question 39

What is move instruction?

Answer 39

MOV Rd, N - Rd: destination register - N: can be an immediate value or source register - mov r7, r5 MVN Rd, N - Move into Rd not of the 32 bit value from source

Question 40

What does the barrel shifter enables?

Answer 40

- Enables shifting 32 bit operand in one of the source registers left or right by a specific number of positions within the cycle time of instruction - Shift left, shift right, rotate right - Facilitates fast multiply, division

Question 41

What is arithmetic instruction?

Answer 41

Implements 32 bit addition and subtraction - SUB r0, r1, r2 - - Subtract value stored in r2 from that of r1 and store in r0.

Question 42

What is arithmetic instruction with barrel shifter?

Answer 42

Increases the set of possible available operations

Question 43

What are multiply instructions?

Answer 43

Multiply contents of a pair of registers - generate 64 bit results

Question 44

What is multiply and accumulate?

Answer 44

``` Result of multiplication can be accumulated with the content of another register. Signal processing - Filtering - Communications - Error control codes ```

Question 45

What is Logical Instructions?

Answer 45

Bit wise logical operations on the two source registers.

Question 46

What is compare instructions?

Answer 46

Enables comparison of 32 bit values, update CPSR flags but do not affect other registers

Question 47

What is data transfer instructions?

Answer 47

- Load/store instructions | - Used to move signed and unsigned Word, Half Word and Byte to and from registers

Question 48

What is Multiple Register Transfer?

Answer 48

- Load-store multiple instructions transfer multiple register contents between memory and the processor in a signal instruction - More efficient for moving blocks of memory and saving restoring context and stack - Increase interrupt latency

Question 49

What are block transfer instructions?

Answer 49

- Load/store multiple instructions (LDM/STM) | - Whole register bank or a subset copied to memory or restored with single instruction

Question 50

What is swap instruction?

Answer 50

Exchanges a word between registers. | - Two cycles but single atomic action

Question 51

How to modify status registers?

Answer 51

- Indirectly - MSR moves contents from CPSR/SPSR to selected GPR - MRS moves contents from selected GPR to CPSR/ SPSR - Only in privileged mode

Question 52

What are control flow instructions?

Answer 52

- Branch instructions - Conditional branches - Conditional execution - branch and link instructions - Subroutine return instructions

Question 53

What is branch instruction?

Answer 53

- B label : address label is stored in the instruction as a signed pc-relative offset - B : Branch has a condition associated with it and executed if condition codes have the correct value

Question 54

What is conditional execution?

Answer 54

The conditional execution applies not only to branches but to all ARM instructions. - Each data processing instruction prefixed by condition code - 16 conditions

Question 55

Data Processing Instructions overview?

Answer 55

Conditional codes + data processing instructions + barrel shifter = powerful tools for efficient coded programs

Question 56

What are the features of ARM instruction set?

Answer 56

- Load/Store architecture - 3 address data processing instruction - Conditional execution - Load/store multiple registers - Shift and ALU operation in single clock cycle.