chapter 3

Question 1

what are the accessing methods for unit data

Answer 1

1. sequential - organized into words and access in a sequential manner
2. direct access - read & write mechanism
   - direct access of data from physical memory
3. random access - has unique addressing mechanism
   - location of address is random (will access from available devices or memory)
4. associative - recognized data by its content than its address

Question 2

explain the importance of cache size

Answer 2

1. access time - large size, large no. of gates, increase addressing, decrease performance
2. cost - small size, increase performance, increase cost
   - larger size, decrease performance, decrease cost

Question 3

what are the access method of cache

Answer 3

1. direct - 1 main memory block mapped to 1 unique cache line
2. fully associative - each memory block can map to any cache line
3. set associative - each memory block map to 1 unique cache line

Question 4

what is replace algorithm

Answer 4

• replace 1 of the existing block with a new one after cache is filled
• 3 types
  1. least recently used - replace block in cache the longest (simple & effective)
  2. first in first out - replace block in cache the longest ( fist to come in first to go out)
  3. least frequently used - replace block has the fewest reference experienced

Question 5

explain write through & write back

Answer 5

through - write operations to main memory & cache

back - updates are only in cache
- io modules are allowed through the cache

Question 6

what’s a cache coherency

Answer 6

transfer of data from caches of different devices with a shared memory
- if 1 data is altered, it will caused an invalidation of data among other caches & main memory
- 3 main approaches
1. bus watching with write through
= use cache controller to monitor address lines by other bus master

2. hardware transparency
   = additional hardware to ensure updates in main memory is reflected in all caches
3. non-cacheable memory
   = more than 1 processor shared memory is designed as non-cacheable memory & access to that memory is considered a cache miss

Question 7

what are the 3 design principles

Answer 7

1. locality 2.inclusion 3.coherence