Chapter 3 Flashcards

(47 cards)

1
Q

An embedded system has three tasks: sensor acquisition, control algorithm, and
communication. Each task must run independently but share CPU time.
Which RTOS concept best supports this design?

A

Threads

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2
Q

Two threads update the same global variable storing sensor data. Occasionally, corrupted
values appear.
What RTOS mechanism should be used to prevent this issue?

A

Mutex

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3
Q

A thread waits indefinitely for a shared resource and blocks the system when the resource
is never released.
Which RTOS feature prevents this situation?

A

Mutex timeout

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4
Q

A control task must execute every 10 ms with guaranteed maximum latency.
Which system property is most critical?

A

Deterministic timing

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5
Q

An RTOS scheduler decides which thread runs next, not the programmer.
What is the main benefit of this approach?

A

Deterministic execution control

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6
Q

A thread has its own stack in an RTOS.
What is the main purpose of this stack?

A

Save execution context

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7
Q

An RTOS guarantees bounded response times and predictable scheduling.
Which statement best describes such an OS?

A

Real-time

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7
Q

Why are mutexes preferred over disabling interrupts for protecting shared data in RTOS
applications?

A

Mutexes allow for safe concurrency

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8
Q

A thread waits up to 100 ms for a mutex. If unavailable, it continues execution.
What RTOS property does this demonstrate?

A

Deterministic behaviour

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9
Q

Which advantage of RTOS-based concurrency most directly improves software
maintainability?

A

Cleaner and modular code

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10
Q

In a multi-threaded RTOS system, only one thread accesses shared data at a time.
What does this ensure?

A

Safe concurrency

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11
Q

In the FreeRTOS firmware stack, user code interacts mainly with:
A. Vendor drivers directly
B. Hardware registers
C. FreeRTOS APIs
D. MCU peripherals

A

C) FreeRTOS APIs

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12
Q

What is the main role of CMSIS in an ARM-based system?

A

Hardware abstraction

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13
Q

Which application is least appropriate for using an RTOS?
A. Multi-protocol gateway
B. Graphical user interface
C. Periodic ADC sampling
D. Networked motor controller

A

C) periodic ADC sampling

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14
Q

Why can bare-metal systems be more deterministic?

A

No scheduler overhead

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15
Q

An RTOS provides the greatest benefit when:
A. Only one task exists
B. Timing is not critical
C. Multiple tasks compete for CPU
D. Code size must be minimal

A

Multiple tasks compete for CPU

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16
Q

Why should ISRs remain short in FreeRTOS systems?

A

To minimize latency because they delay task scheduling.

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17
Q

Which design best improvides portability across ARM MCUs?
A. Direct register access
B. Vendor-specific HAL only
C. CMSIS with FreeRTOS
D. Inline assembly

A

C) CMSIS with FreeRTOS

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18
Q

When a higher-priority task becomes ready, FreeRTOS will:

A

Preempt the current task

19
Q

Why is bare-metal often chosen for encoder-based motion control?

A

Lower overhead

20
Q

Which factor is least relevant when choosing an RTOS?
A. Real-time constraints
B. Available memory
C. Team expertise
D. Screen resolution

A

D) Screen resolution

21
Q

What is the common property of all embedded
systems?
a) They rely on RTOS for execution.
b) They have a defined exit point.
c) They are designed for desktop environments.
d) They run continuously without an exit point

A

d) They run continuously without an exit point

22
Q

What is a potential drawback of super loops in real-time systems?

A

Delays in one function propogate to the next.

23
Q

What is jitter in the context of super loops?

A

The variability in delay for detecting an event/the variation in response time

24
Which hardware is essential for handling interrupts in ARM Cortex-M cores?
Nested Vector Interrupt Controller (NVIC)
25
What is the role of an Interrupt Service Routine (ISR)?
To handle events with minimal delay
26
What is the advantage of Direct Memory Access (DMA)?
It reduces CPU involvement in data transfer.
27
When is an RTOS not required for a system?
When the system has limited repsonsibilities.
28
What does preemptive scheduling ensure in a system?
The most critical task gets the CPU when needed.
29
What problem does task starvation represent in preemptive scheduling?
Lower-priority tasks not getting CPU time
30
What is a primary benefit of using RTOS tasks over super loops?
Better responsiveness in complex systems
31
What is the role of a scheduler in round-robin scheduling?
It assigns equal CPU time slices to tasks
32
How does FreeRTOS reduce overhead during task switching?
By implementing an efficient kernel.
33
What feature of ARM Cortex-M processors minimizes latency for nested interrupts?
Interrupt-tail chaining.
34
What happens if a task in a super loop takes too long to execute?
It delays the execution of subsequent tasks
35
In a basic super-loop, what mainly dtermines the worst-case response time to an external event?
The duration of the entire loop
36
Why does polling reduce efficiency in embedded systems?
It wastes CPU time when no event occurs.
37
What is the main reason ISRs should be kept short?
To minimize latency and jitter
38
What NVIC feature most directly improves real-time behaviour?
Configurable interrupt priorities.
39
What is the main real-time benefit of using DMA?
Lower CPU involvement
40
In a super-loop combined with interrupts, what should the ISR primarily do?
Set a flag and return
41
Why does each RTOS task have its own stack?
To prevent stack interference
42
In a preemptive RTOS, which task executes when multiple tasks are ready?
The one with highest priority
43
Which condition most strongly justifies choosing an RTOS over a super-loop?
Strict timing guarantees
44
Which of the following resources is NOT shared between tasks in a preemptive RTOS? A. Global variables B. Heap memory C. Peripheral registers D. Task stack
D) Task stack
45
Which sequence best represents the typical steps of a task context switch in a preemptive RTOS? A. Save current task context → select next task → restore next task context B. Disable interrupts → execute ISR → resume task C. Switch stack pointer → restart scheduler → clear registers D. Update priority → flush cache → resume execution
A. Save current task context → select next task → restore next task context
46
When an interrupt occurs, which sequence best describes how the CPU responds? A. Complete instruction → save context → jump to ISR B. Stop execution → clear registers → run ISR C. Disable scheduler → switch task → run ISR D. Save stack → update priority → resume task
A. Complete instruction → save context → jump to ISR