1
Q
What is a clock?
A
A clock drives the steps in the processor - everything happens on the clock “edge” as systems are synchronous
2
Q
What does the Program Counter do?
A
Contains the address of the instruction to run
Increments after each instruction
3
Q
What does the Instruction Register do?
A
Contains the instruction most recently fetched
4
Q
What does the Memory address register do
A
Contains the address of a location in memory
5
Q
What does the Memory buffer register do?
A
Contains a word of data to be written to memory or the word most recently read
6
Q
What happens in the fetch part of the fetch-execute cycle?
A
- PC contains address of next instruction
- Address moved to MAR
- Address placed on address bus
- Control unit request memory read
- Result placed on data bus, copied to MBR, then to IR
- PC incremented by 1
7
Q
What happens in an indirect fetch cycle?
A
it fetches the data stored in the memory location, to use the data to fetch/reach the memory location of the data required
8
Q
Advantages of Von Neumann?
A
Simple - data and instructions stored in a single memory space
Cost-Effective - Smaller number of components
9
Q
Disadvantages of Von Neumann
A
Bottleneck - Shared bus, simultaneous obtaining impossible
Memory Corruption - same memory space, erase
10
Q
Advantages of Harvard
A
Faster processing - Two buses
Improved Security - Not stored in same location, no erase
Efficient use of resources
11
Q
Disadvantages of Harvard
A
Complexity - intricate design
Higher cost
Less Flexibility
12
Q
RISC characteristics
A
- Instructions of fixed length in a single clock cycle
- Pipelines to achieve one-instruction-per-one-clock-cycle
- Simple control logic to increase clock speed
- Operations performed on internal registers (load store instructions access external memory only)
13
Q
CISC characteristics
A
- Binary compatibility (old binary code on newer systems)
- Complex control logic
- Use of micro-code
- Variable length instructions to save program memory
- Small internal register sets compared with RISC
- Complex addressing modes, operands can reside in external memory or internal registers
14
Q
What is pipelining?
A
Pipelines overlap operations to aim to complete an instruction every clock cycle
15
Q
What are the different ways of branch prediciton?
A
- Multiple streams
- Prefetch Branch Target
- Loop buffer
- Branch prediction
- Delayed branching
16
Q
How does multiple streams work in pipelining?
A
- Have two pipelines
- Prefetch each branch into a separate, appropriate pipeline
- Waste the branch you didn’t need
17
Q
Disadvantages of Multiple streams
A
- Leads to bus & register
- Multiple branches lead to further pipelines being needed
18
Q
How does Prefetch Branch Target work?
A
- Target of branch is prefetched in addiction to instructions following branch
- Keep target until branch is executed
19
Q
How does Loop Buffer work?
A
- Stores all the instructions of a loop in a buffer in the CPU
- Optimises the process of jumping away from the previous instruction
- Check buffer before fetching from memory
20
Q
How does Static Branch Prediction work?
A
- Predicts one side (jump or not jump)
- If no jump, always fetch next instruction
-If jump, fetch target instruction
21
Q
How would Branch Predicition be improved?
A
- Predict using the opcode
- Produce Statistics related to the likely hood of jumping
- Can learn
22
Q
What is a superscalar processor?
A
A processor that completes more than one instruction per clock cycle
23
Q
What is In-Order Issue, Completion?
A
- Issue instructions in the order they occur
- May fetch >1 instruction
24
Q
Disadvantages of In-order Issue, Completion
A
- Not very efficient
- Instructions must stall if necessary
25
What is True Data Dependency?
It can execute fetch and decode two instructions simultaneously but not execute the second because it is dependent on the first
26
What is Procedural Dependency?
Can not execute instructions after a branch in parallel with instructions before a branch, preventing simultaneous fetches
27
What is Resource Conflict?
Two or more instructions requiring access to the same resource at the same time
28
What is Out-of-Order Issue, Completion?
- Decouple decode pipeline from execution pipeline
- Can continue to fetch and decode until this pipeline is full
- When a functional unit becomes available, an instruction can be executed
29
What is an Antidependency?
A register value is needed but changed in the next instruction
30
What is an Instruction Set?
The structure of a computer that a machine language programmer must understand to write a correct program for that machine
31
What is opcode?
The operation code is the instruction/task that has to be completed
32
What is the operand reference?
Where the data is referenced, the item of data is used from there
33
What is the result reference?
Where the instruction output gets put
34
What does the ALU do?
It does the arithmetic and logic operations in the CPU. It can also shift or rotate bits
35
What is the benefit of more addresses per instruction?
- More complex (powerful?) instructions
- More registers
- Register-to-Register operations are quicker
- Fewer instructions per program
36
What is the benefit of fewer addresses per instruction?
- Less complex instructions
- More instructions per program
- Faster fetch/execution of instructions
37
What is the important of data alignment?
Reading miss-aligned data may need multiple memory reads and shift which will negatively effect performance
38
What is Endianness
How are bytes in a word ordered and how are bits in a byte ordered
39
How are bytes ordered in big endian?
Most significant byte in the lowest numerical address
40
How are bytes stored in little endian?
The least significant byte in the lowest numerical address
41
What are characteristics of big endian?
- Memory dumps left to right (easy for western audiences)
- Big endian machines store character strings and integers in the same order
- Has to perform an extra operation (addition) when converting from 32 to 16 bit address
42
What is the main 5 instruction set architectures?
- Accumulator based
- Stack based
- Register-memory based
- Register-register
- Memory-Memory
43
How does Accumulator ISA work?
A value is loaded into the accumulator and another is added directly from memory with the result stored in accumulator
44
How does Stack based ISA work?
- Both operands pushed onto the stack
- The result is popped off the stack
45
How does Register-memory ISA work?
- One input is loaded from memory
- It gets added to by a value put into a register and the result is stored in a register
LOAD R3, A
ADD R1, R3, B
STORE R1, X
46
How does Register-Register ISA work?
- Operands are loaded from memory to registers
- Add uses the operands stored in registers
47
Advantages of Accumulator ISA
- Short Instructions
- One implicit operand, one explicit
48
Disadvantages of Accumulator ISA
- Single temporary storage location
- High memory traffic
49
Advantages of Stack ISA
- Simple model
- Short instructions
- Implicit operands
50
Disadvantages of Stack ISA
- The stack cannot be randomly accessed
- Stack becomes a bottleneck
51
Advantages of Register ISA
- Easy code generation
- Clever compiler optimisations
- Fast access to temporary values
52
Disadvantages of Register ISA
- Operands must be named
- Longer instructions
53
Advantages of Register-Memory
- Simple code generation
- Data can be accessed directly
54
Disadvantages of Register-Memory
- Functionally commutative operations, non-commutative behaviour
- Instructions require a variable number of cycles
55
Advantages of Register-Register
- Fixed-size instructions
- Simple code generation
- (Most) instructions require a similar, known number of cycles
- Fast
56
Disadvantages of Register-Register
High instruction count
57
Advantages of Memory-Memory
Produces compact code
58
Disadvantages of Memory-Memory
- Large variation in instruction size
- Large variation in execution time per instruction
- Memory access is the bottle neck
No longer used
59
What is Memory Connection?
- Consists of N words of equal length with unique address
- Memory receives addresses and receives control signals (Read, Write, Timing) and sends data
60
What is a CPU connection
- Reads instruction and data
- Sends control signals to other units
- Receives and acts on interrupts
61
What is a shared bus?
A common communication pathway
62
What does the address bus do?
Identify the source or destination of data
63
What does the Control bus do?
Control and timing of information
64
What are the typical control lines?
- Memory read/write signal
- I/O Port read/write signal
- Transfer Acknowledgement
- Bus request/grant
- Interrupt request/acknowledgement
- Clock signals
- Reset
65
What issues are caused by a single bus?
- Propagation delays, different devices may work at different speeds
66
Why is Timing import with interconnects and buses?
- Coordination of events on bus
- Normally Synchronous as events are determined by clock signals
67
What is the PCIe (Peripheral Component Interconnection express)?
A serial bus with multi- GiByte/s "lanes" where the speed depends on the version. it uses more lanes for a GPU card
68
How does a module use a bus?
- Obtain the use of the bus
- Transfer data and/or requests
- Synchronise and/or acknowledge
69
What does the PCIe do?
High-speed serial computer expansion bus standard. It is like a network with layers and addressing
70
What is SAS (Serial attached SCSI)?
- Very fast serial SCSI, compatible with latest SATA
- Very flexible due to the layers of the protocol
71
What are characteristics of a USB?
- Ideal for low-speed to high I/O devices
- Expandable as it is simple design and configuration that allows up to 127 devices
72
What are the elements of a USB's hardware?
- Assumes a root hub connected to the main bus
- Cable contains four wires
- Data transmitted as 0 for a voltage transition and 1 as the absence of one
73
What are the four kind of USB frame signals?
- Control
- Isochronous (For real time devices where data should be sent/received at precise intervals)
- Bulk
- Interrupts (Used for regular polling of devices)
74
What do motherboard interconnects do?
- High speed links to chipset from one or more CPU packages
- Links are very similar to PCIe
75
What is a chiplet?
Putting lots of chips together
76
What is a chipset?
A set of electronic components on one or more integrated circuits that manages data flow
77
What is UPI (UltraPath Interconnect)
- Intel's proprietary high speed link
- Point to point link between CPU chips and to chipset
- Handles cache-coherency
- Around 20GiB/s per link
78
What is BIOS (basic input/output system)?
- Firmware on the motherboard
- Hardware initialisation
- Booting
79
Where is BIOS stored?
In Flash memory
79
What does BIOS do?
- Used for I/O functions in MS-DOS to help standardise PCs
- finds a boot loader on disk/CD/USB
- Loads first sector of disk into RAM
80
What is UEFI (Unified Extensible Firmware Interface) ?
Replaces old BIOS and connects a OS to its firmware
81
What is Flynn's Taxonomy?
Classification of computer architectures
82
What is SISD?
Single Instruction Single Data
83
What is MISD?
Multiple Instruction Single Data
84
What is SIMD?
Single Instruction Multiple Data
85
What is MIMD?
Multiple Instruction Multiple Data
86
What does SIMD need?
Special hardware i.e. Streaming SIMD Extensions and special software
87
What is SSE used for?
- Image processing
- Video processing
-array/vector processing
- text processing
- General speed-up
88
What is SIMD used for?
Cuda and GPU processing
89
What is SMP (Symmetric Multiprocessors)?
- A MIMD System that has multiple CPUs share main memory and I/O
- The hardware manages contention and increases the performance especially multiuser/thread
90
How does a Typical SMP system work?
- Each processor has its own L1 and L2 cache
- Connected by a system bus, crossbar switch or other interconnect
- Main memory, I/O, etc are also connected to the interconnect
91
What is Heterogenous Multi-processing?
- Combine big performance cores with little energy efficient cores
- "Big" cores only used when performance is necessary, "little" cores used for most tasks
- Needs operating system support to fully leverage
92
What is Simultaneous multithreading (SMT) / Hyper-threading?
- Hardware multi-threading on superscalar CPUs
- Executes multiple instructions at the same time using redundant execution units in the processor
93
What is Data parallelism?
Split the data to make independent parallel tasks
94
Computer Systems
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