CSO5 MIPS DATAPATH

Question 1

SINGLE-CYCLE MIPS

Answer 1

• memory reference
  -arithmetic and logic
  -control flow
  instructions
  pc(program counter) for instruction address
  mem->read/write register file-> execute
  1 cycle 32-bit alu instructions

1. IF - instruction fetch: send pc counter and fetch instruction
2. ID - instruction decode: decode instruction and read regs
3. EX - execution: reconfiguration of hw depending on instruction type using multiplexers
   4.MEM-WB - memory writeback: read/write in mem components

Question 2

INSTRUCTION FETCH

Answer 2

CPU is infinite loop
-gets instruction from instruction memory
-updates pc with address of next instruction
instruction memory and pc are always active

Question 3

INSTRUCTION DECODING

Answer 3

-parse registers
-read 2 at a time
-write when regWrite =1

memory access is slow (takes multiple cycles) thats why we use cache memory-registers 1 and 2 cycle cache for instruction data

Question 4

R-TYPE EXECUTION

Answer 4

fetch->decode->do alu operation and write data to register

op rs rt rd shift amount function

pc (after it goes to instruction memory we add 4 to get the next instruction
->instruction memory
-> register file get rs rt rd
-> feed rt rd to ALU and perform operation
-> store in register rs

Question 5

I-TYPE MEMORY INSTRUCTIONS EXECUTION

Answer 5

-memory reference instructions:
op rs rt i
pc (after it goes to instruction memory we add 4 to get the next instruction
->instruction memory
-> register file get rs rt
->

Question 6

BRANCH INSTRUCTIONS

Question 7

DATAPATH

Question 8

MIPS SINGLE-CYCLE DATAPATH