Datapaths

Question 1

RTN(s) for the TRAP instruction

Answer 1

R7 ⇐ PC; PC ⇐ Mem[ ZEXT(IR[7:0]) ]

Question 2

RTN(s) for the JMP instruction

Answer 2

PC ⇐ BaseR

Question 3

RTN(s) for the ADD instruction - register mode -

Answer 3

DR ⇐ SR1 + SR2

Question 4

RTN(s) for the ADD instruction - immediate mode -

Answer 4

DR ⇐ SR1 + SEXT(IR[4:0])

Question 5

RTN(s) for the AND instruction - register mode -

Answer 5

DR ⇐ SR1 . SR2

Question 6

RTN(s) for the AND instruction - immediate mode -

Answer 6

DR ⇐ SR1 . SEXT(IR[4:0])

Question 7

RTN(s) for the JSR instruction

Answer 7

R7⇐PC; PC ⇐ PC + SEXT(IR[10:0])

Question 8

RTN(s) for the NOT instruction

Answer 8

DR ⇐ (SR1’)

Question 9

RTN(s) for the ST instruction

Answer 9

Mem[ PC + SEXT(IR[8:0]) ] ⇐ SR

Question 10

RTN(s) for the LD instruction

Answer 10

DR ⇐ Mem[ PC + SEXT(IR[8:0]) ]

Question 11

RTN(s) for the LDR instruction

Answer 11

DR ⇐ Mem[ IR[8:6] + SEXT(IR[5:0]) ]

Question 12

RTN(s) for the LEA instruction

Answer 12

DR ⇐ PC + SEXT(IR[8:0])

Question 13

RTN(s) for the STI instruction

Answer 13

Mem[ Mem[ PC + SEXT(IR[8:0]) ] ] ⇐ SR

Question 14

RTN(s) for the BR instruction

Answer 14

PC ⇐ PC + SEXT(IR[8:0]) iff (N.n + Z.z + P.p)

Question 15

RTN(s) for the STR instruction

Answer 15

Mem[ IR[8:6] + SEXT(IR[5:0]) ] ⇐ SR

Question 16

RTN(s) for the JSRR instruction

Answer 16

R7 ⇐ PC; PC ⇐ (BaseR)

Question 17

Control Instructions for BR

Answer 17

1. ADDR1MUX selects PC
2. ADDR2MUX selects SEXT(IR[8:0])
3. PCMUX selects ADDR ADD
4. LD.PC iff (N.n + Z.z + P.p)

Question 18

Control Instructions for JSRR

Answer 18

1. GatePC
2. DRMUX selects [111]
3. LD.REG
4. SR1MUX selects IR[8:6] ​
5. ADDR1MUX selects SR1OUT
6. ADDR2MUX selects 0
7. PCMUX selects ADDR ADD
8. LD.PC

Question 19

Control Instructions for TRAP

Answer 19

1. GatePC
2. DRMUX selects [111]
3. LD.REG
4. MARMUX selects ZEXT(IR[7:0)
5. Gate.MARMUX
6. LD.MAR
7. MEM.EN/R
   a. Wait for R
8. MDRMUX selects MEM.​
9. LD.MDR
10. Gate.MDR​
11. PCMUX selects bus.
12. LD.PC

Question 20

Control Instructions for LDR

Answer 20

1. SR1MUX selects IR[8:6]
2. ADDR1MUX selects SR1OUT
3. ADDR2MUX selects SEXT(IR[5:0])
4. MARMUX selects ADDR ADD
5. Gate.MARMUX
6. LD.MAR
7. MEM.EN/R
   a. Wait for R
8. MDRMUX selects Memory
9. LD.MDR
10. Gate.MDR ​
11. DRMUX selects IR[11:9] ​
12. LD.REG

Question 21

Control Instructions for ST

Answer 21

1. ADDR1MUX selects PC
2. ADDR2MUX select SEXT(IR[8:0])
3. MARMUX selects ADDR ADD
4. Gate.MARMUX
5. LD.MAR
6. SR1MUX selects IR[11:9]
7. ALUK selects Pass Through
8. Gate.ALU
9. MDRMUX selects bus ​
10. LD.MDR
11. MEM.EN/W

Question 22

Control Instructions for STI

Answer 22

1. ADDR1MUX selects PC
2. ADDR2MUX selects SEXT(IR[8:0])
3. MARMUX selects ADDR ADD
4. Gate.MARMUX
5. LD.MAR
6. MEM.EN/R
   a. Wait for R
7. MDRMUX selects Memory
8. LD.MDR
9. Gate.MDR
10. LD.MAR
11. SR1MUX selects IR[11:9]
12. ALUK selects Pass Through
13. Gate.ALU
14. MDRMUX selects Bus
15. LD.MDR
16. MEM.EN/W

Question 23

Control Instructions for STR

Answer 23

1. SR1MUX selects IR[8:6]
2. ADDR1MUX selects SR1OUT
3. ADDR2MUX selects SEXT(IR[5:0])
4. MARMUX selects ADDR ADD
5. Gate.MARMUX
6. LD.MAR
7. SR1MUX selects IR[11:9]
8. ALUK selects Pass Through
9. Gate.ALU
10. MDRMUX selects Bus
11. LD.MDR
12. MEM.EN/W

Question 24

Control Instructions for JMP/RET

Answer 24

1. SR1MUX selects IR[8:6]
2. ADDR1MUX selects SR1OUT
3. ADDR2MUX selects 0
4. PCMUX selects ADDR ADD
5. LD.PC

Question 25

Control Instructions for JSR

Answer 25

1. GatePC 2. DRMUX selects [111] ​ 3. LD.REG 4. ADDR1MUX selects PC 5. ADDR2MUX selects SEXT(IR[10:0]) 6. PCMUX selects ADDR ADD 7. LD.PC

Question 26

Control Instructions for JSRR

Answer 26

1. GatePC 2. DRMUX selects [111] ​ 3. LD.REG 4. SR1MUX selects IR[8:6] ​(not shown in the simplified datapath) 5. ADDR1MUX selects SR1OUT 6. ADDR2MUX selects 0 7. PCMUX selects ADDR ADD 8. LD.PC

Question 27

Control Instructions for TRAP

Answer 27

1. GatePC 2. DRMUX selects [111] ​ 3. LD.REG 4. MARMUX selects ZEXT(IR[7:0) 5. Gate.MARMUX 6. LD.MAR 7. MEM.EN/R a. Wait for R 8. MDRMUX selects MEM.​ 9. LD.MDR 10. Gate.MDR​ 11. PCMUX selects bus. 12. LD.PC

Question 28

Control Instructions for ADD (register mode)

Answer 28

1. SR1MUX selects IR[8:6] 2. SR2MUX selects SR2OUT 3. ALUK selects ADD 4. GateALU 5. DRMUX selects IR[11:9] 6. LD.REG

Question 29

Control Instructions for ADD (immediate mode)

Answer 29

1. SR1MUX selects IR[8:6] 2. SR2MUX selects SEXT(IR[4:0]) 3. ALUK selects ADD 4. GateALU 5. DRMUX selects IR[11:9] 6. LD.REG

Question 30

Control Instructions for AND (register mode)

Answer 30

1. SR1MUX selects IR[8:6] 2. SR2MUX selects SR2OUT 3. ALUK selects AND 4. Gate.ALU 5. DRMUX selects IR[11:9] 6. LD.REG

Question 31

Control Instructions for NOT

Answer 31

1. SR1MUX selects IR[8:6] ​ 2. ALUK selects NOT 3. Gate.ALU 4. DRMUX selects IR[11:9] 5. LD.REG

Question 32

Control Instructions for LEA

Answer 32

1. ADDR1MUX selects PC 2. ADDR2MUX selects IR[8:0] 3. MARMUX selects ADDR ADD 4. Gate.MARMUX 5. DRMUX selects IR[11:9] 6. LD.REG

Question 33

Control Instructions for LD

Answer 33

1. ADDR1MUX selects PC 2. ADDR2MUX selects SEXT(IR[8:0]) 3. MARMUX selects ADDR ADD 4. Gate.MARMUX 5. LD.MAR 6. MEM.EN/R a. Wait for R 7. MDRMUX selects Memory 8. LD.MDR 9. Gate.MDR 10. DRMUX selects IR[11:9] 11. LD.REG

Question 34

Control Instructions for LDI

Answer 34

1. ADDR1MUX selects PC 2. ADDR2MUX selects SEXT(IR[8:0]) 3. MARMUX selects ADDR ADD 4. Gate.MARMUX 5. LD.MAR 6. MEM.EN/R a. Wait for R 7. MDRMUX selects Memory 8. LD.MDR 9. Gate.MDR 10. LD.MAR 11. MEM.EN/R a. Wait for R 12. MDRMUX selects Memory 13. LD.MDR 14. Gate.MDR 15. DRMUX selects IR[11:9] 16. LD.REG