Discretization: Sample-and-hold Circuits
Clockes transistor + capacitor (V3 p. 21)
Transistor: open or closed at sampling times
Capacitor: stores sequence values
Aliasing - Nyquist Criterion, fn, fs?
Aliasing occurs when the sampling time is to low and therefore information gets lost.
Nyquist Criterion: Aliasing can be avoided if we restrict the frequencies of the incoming signal to less than half of the sampling rate.
ps < 0.5pn, where pn is the period of the “fastest” sine
fs > 2fn, where fn is the freq. of fastes sine wave
fn called Nyquist frequency, fs is sampling rate
Anti-Aliasing Filter
Is used to remove high frequencies (kind of low pass filter) —> cuts out all frequencies higher than fs/2
e(t) —> anti aliasing g(t) —-> sample and hold h(t)
A/D Converter, name two with specification
Flash A/D Converter:
- resolution is number of intervals of Vref (Spannungsteiler mit Komparatoren)
- fast but hardware complexity large
Successive Approximation (“educated guessing”):
- convert digital values back to analog to compare them again with input
- test highest bit (most significant bit) first, if too large = 0, then check next bit until least significant bit
- slow but only one comparator needed and high precision
Energy vs. Power Consumption
When do you want to minimize what?
Power Consumption:
- Design of the power supply and regulators
- Dimensioning of interconnect, short term cooling
Energy Consumption (Power over time):
- Restricted availability of energy (mobile devices)
- cooling: high cost, limited space
- thermal effects
- dependability, long lifetimes
Solution for Energy- and Perfomance Demands are very high?
ASIC (Application-Specific Integrated Circuit
-> but high development cost, long design times and lack of flexibility
Dynamic Power Consumption?
How to make the power consumption more efficient and what happens to the speed?
- Power consumption caused by charging capacitors when logic levels are switched
- reducing Vdd results in a quadratic reduction of power but only linear decrease of speed (clock freq.) (V3 p. 49)
P ~ Vdd^2
f ~ Vdd
Multicore structure main advantage?
Time (faster) and therefore energy consumption.
The longer the processesor core is not in idle, the more energy is needed. Dividing many tasks on multiple cores results in less energy (power over time).
Static Power Consumption?
- caused by leakage current -> power consumed in absence of clock signals
- leakage becoming more important due to smaller devices
Power Consumption: Heterogeneous Processors?
Switching between different size of cores. (ie. in a quadcore)
Key point: they must be binary compatible (same machine code)
Code Efficiency: Dictionary Approach
- Indirect addressing of instructions
- storage for dictionary needed
- all same instruction are mapped with dictionary bits
- -> instructions take more space than dictionary bits in memory
Code Efficiency: Code Compression
- 2nd instruction set, which are smaller
- dynamically encoded at runtime
- reduction of ~70% of original code size
–> good performance of processor - memory connection is mandatory (32bit memory worse than 8/16bit memory)
Digital Signal Processors: Heterogeneous Registers
- Functionality of registers divided to different task in parallel –> efficient run time
- Load input data, load filter coefficient, pointer arithmetic
Digital Signal Processors:
Classical machine loops vs Zero-Overhead Loops (ZOL)
Classical: loop counter initialized -> do stuff -> decrement counter -> jmp if decrement !Zero
RATHER INEFFICIENT
ZOL: No jumps used, LOOP instruction used without overhead and disturbance of internal processor pipeline
Digital Signal Processors: Multiple/Accumulate (MAC)
MAC: Ability to fetch two operands (current input and current filter coefficient) at the same time –> efficient
Calculation and Accumulating in one operation (MADD instruction)
Digital Signal Processors: AGUs
- pointer arithmetic in the AGUs (Address Generation Units) usually only: pointer++ (jump bytewise through registers)
Digital Signal Processors: Modulo Addressing
- implements a circular buffer in memory with only the last n recent values
- new value overrides oldest value
Digital Signal Processors: Saturating Arithmetic
- if a calculation leads to a overflow/wrap around
- expl: 1101 + 0011 would usually be 10000
but only 4 bits are available -> saturating arithmetic causes result to be 1111 (saturated at maximum)
Digital Signal Processors: What makes them Real-time capable?
- timing behavior has to be predictable therefore following features are not included:
- unpredictable access to shared ressources (caches with certain replacement strategies, unified caches, pipelines with difficult to predict stall cycles, multiprocessors with unpredictable communication)
- branch prediction, speculative execution
- interrupts possible at any time
- memory refreshes possible at any time
- instructions which have data-dependent execution times
TRY TO AVOID AS MANY AS POSSIBLE FROM ABOVE
What is a Reconfigurable Logic? Application Examples?
- custom hardware too expensive, software too slow
–> combination of speed of hardware and flexibility of software: Configurable Hardware!
Common example: FPGAs (Field-programmable Gate Arrays) - FPGAs implement truth tables/lookup tables
Applications:
- algorithms like de-/encryption
- pattern matching in bioinformatics
- high speed event filtering
- high speed special purpose hardware
Scratch Pad Memory?
- for real time systems better than a cache (to do run time analysis)
- reduces time to load to processor and therefore energy consumption
- energywise better than cache
Memory Efficiency in Embedded Systems?
- energy consumption
- speed
- capacity
memory size + leads to energy consumption +
CSMA/CD vs. CSMA/CA
in real time systems?
Carrier-Sense Multiple-Access / Collision Detection
–> after collision on bus retries –> no guaranteed response time (variants of Ethernet)
NO REAL time use
Carrier-Sense Multiple-Access / Collision-Avoidance
- each partner gets ID (priority) –> after bus transfer partner try setting their ID –> higher ID has higher chance of sending (WLAN techniques)
Not really usable in real time systems, only highest prio device
TDMA Busses?
Time Division Multiple Access Busses
- each communication partner is assigned a fixed time slot
- deterministic timing behavior
