Exam 2 Flashcards

(20 cards)

1
Q

Memory

A

A grid of storage cells (latches or flip-flops) organized into addressable locations.

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2
Q

Address Lines

A

The input that selects which location to read from or write to.

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3
Q

Data Lines

A

Carry the actual data being written (D_in) or read (D_out)

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4
Q

Write Enable (WE)

A

Control line specifies the operation: Read (WE = 0) or Write (WE = 1)

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5
Q

Addressability

A

The number of bits stored in each location (the memory “width”). Common addressability is 8 bits (a byte).

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6
Q

Address Space

A

The total number of unique locations. For a memory with N address lines, the address space is 2^N.

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7
Q

Decoder

A

Its job is to take the binary address and activate a single “word line” corresponding to that address.

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8
Q

Control Unit

A

Coordinates and directs the operation of the computer by using a FSM and clock. It manages the program counter (PC) and instructor register (IR) to control instruction flow and execution.

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9
Q

Processing Unit

A

Contains the Arithmetic Logic Unit (ALU) for performing calculations and the register file for storing operands, improving performance by reducing memory accesses.

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10
Q

Memory Unit

A

Stores data and programs while serving as the interface for all input/output operations between the computer and external devices.

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11
Q

Opcode

A

A code that identifies the operation

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12
Q

Registers

A

The id number of each source register, up to two, and destination register.

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13
Q

Immediate

A

A binary value, usually two’s complement, that is stored directly in the instruction and therefore available immediately.

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14
Q

Fixed Bits

A

Some instructions can be represented without using all of the bits. The ISA will define these bits to be specific values .

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15
Q

Execution Cycle

A

Fetch, Decode, Execute, Memory Writeback, Register Writeback

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16
Q

Fetch

A

The control unit retrieves the next instruction from memory using the address in the program counter (PC) and stores it in the instruction register (IR) for processing.

17
Q

Decode

A

The control unit interprets the instruction in the IR and reads any required operands, preparing the system for the correct execution steps based on the instruction type.

18
Q

Execute

A

The ALU performs the operation specified by the instruction, producing a result or preparing for memory access.

19
Q

Memory Writeback

A

Handles data transfer between the processor and data memory, executing load or store operations as needed to retrieve or save data

20
Q

Register Writeback

A

Writes the final result of the operation into the destination register and updates the program counter (PC) to point to the next instruction.