What are the two wires in I2C?
> SDA (Data)
> SCL (Clock)
How long is a packet?
8 bits
How is each bit transferred over SDA?
On a clock edge
What is the start sequence?
SDA goes low while SCL goes high
What is the stop sequence?
SDA goes high while SCL goes low
What is the general structure for a 1-byte tranaction?
[Picture2]
How does the receiver acknowlege a bit has been recieved?
By holding the SDA line LOW for one clock cycle
How long is an I2C address?
7-bits
What is the 8th bit when an address is being sent?
The direction. 0 = writing 1 = reading e.g. AAAAAAA1
What is the process for reading from a slave?
What type of architecture is I2C?
Master-slave
How many slaves can be connected to an I2C bus?
2^7 - 1 = 127
What is address 0 on an I2C bus?
Used to address all slaves
What can also limit the number of slaves on an I2C bus?
Number of devices is limited by capacitive loading of the lines
What makes I2C more robust than UART?
Because it has acknowlegments
What is the process for reading multiple values from a slave?
It is possible to read a burst of values from multiple registers if the slave is configured to do so.
If the master continues to clock the SCL line then the slave will continue sending data
What is the process for writing values to a slave?
What is the process for writing multiple values to a slave?
This is done in a similar way to burst reading