Latch-up

Question 1

What is latch-up? What problems does it cause?

Answer 1

Shorting of vdd and vss through the ON parasitic bipolar junction transistors which are inherent in CMOS devices. Leads to overheating, permanent physical damage to the silicon, functional failure of the chip, or excessive supply current consumption.

Question 2

How to reduce the chances of latch-up?

Answer 2

1. Taps and guard rings. Stabilize the nwell and psub potentials, and absorb injected carriers, reducing chances that BJTs will wake up.
2. Keep PMOS away from NMOS. Reduces gain of BJTs. If gain is smaller than 1, they are too weak to generate the latch-up current. More commonly adopted in layout of large transistors along edge of chip.
3. Drivers with added slew. Reduces ground-bounce, which reduces injected carriers.
4. Avoid radiation.
5. SOI technology.

Question 3

What does SOI stand for, and what is it?

Answer 3

Silicon-on-insulator. Uses deep trench and buried oxide techniques to isolate devices. Fixes latch-up, as well as junction leakage current due to high temp, such as auto industry. ntaps and ptaps not necessary.

Question 4

What is the alternative to SOI?

Answer 4

“Bulk technology”, our class standard