High-end microprocessors have ___ on-chip cache
> 10 MB
When a word is not found in the cache, a ____ occurs
miss
Immediately update lower levels of hierarchy
Write-through
Only update lower levels of hierarchy when an updated block is replaced
Write-back
Fraction of cache access that result in a miss
Miss rate
Causes of Misses: First reference to a block
Compulsory
Causes of Misses: Blocks discarded and later retrieved
Capacity
Causes of Misses: Program makes repeated references to multiple addresses from different blocks that map to the same location in the cache
Conflict
True or False: Speculative and Multithreaded Processors may execute other instructions during a miss to reduce performance impact of misses
True
Six basic cache optimizations: It reduces compulsory misses
Larger block size
Six basic cache optimizations: Increases hit time and power consumption
Larger total cache capacity to reduce miss rate
Six basic cache optimizations: Reduces conflict misses
Higher Associativity
Six basic cache optimizations: Reduces overall memory access time
Higher number of cache levels
Six basic cache optimizations: It reduces miss penalty
Giving priority to read misses over writes
Six basic cache optimizations: Reduces hit time
Avoiding address translation in cache indexing
Performance metric concerned with cache
Latency
Performance metric concerned with multiprocessors and I/O
Bandwidth
Time between read request and when desired word arrives
Access Time
Minimum time between unrelated requests to memory
Cycle Time
It has low latency and is used for cache
SRAM memory
Use for main memory
DRAM
SRAM requires ______ to retain bit and _ _________/bit
low power; 6 transistors
DRAM must be ____ after being read, and be periodically _____.
re-written; refreshed
How many transistor per bit in DRAM?
1
