1
Q
Register Latency
A
Lowest
2
Q
Register Volatile
A
Yes
3
Q
Register 2^k capacity
A
Y
4
Q
Register Cost/Bit
A
Highest
5
Q
Register Density
A
low
6
Q
Register location
A
In Processor
7
Q
Register Controller complexity
A
lowest (mux)
8
Q
SRAM Latency
A
2nd lowest
9
Q
SRAM Volatile
A
Yes
10
Q
SRAM 2^k capcity
A
Yes
11
Q
SRAM Cost / bit
A
2nd highest
12
Q
SRAM density
A
higher (than Register)
13
Q
SRAM location
A
On processor chip
14
Q
SRAM Controller Complexity
A
low (mux)
15
Q
DRAM Latency
A
3rd lowest
16
Q
DRAM Volatile
A
Yes
17
Q
DRAM 2^k Capcity
A
Yes
18
Q
DRAM Cost / bit
A
3rd highest
19
Q
DRAM density
A
higher still (than SRAM)
20
Q
DRAM location
A
off CPU chip, but close
21
Q
DRAM Controller complexity
A
mux + refresher
22
Q
Flash Latency
A
very high
23
Q
Flash Volatile
A
No
24
Q
Flash 2^k capcity
A
Yes
25
Flash Cost / bit
highest non-volatile
26
Flash density
higher still (than DRAM)
27
Flash location
Off CPU chip, but likely close
28
Flash controller complexity
Complex!!!
29
Magnetic Disk latency
"glacial" (very very high)
30
Magnetic Disk volatile
No
31
Magnetic Disk 2^k capacity
No
32
Magnetic Disk cost / bit
middle non-volatile
33
Magnetic Disk density
very high
34
Magnetic Disk location
"Where's Waldo??" (Doesn't matter)
35
Magnetic Disk controller complexity
complex
36
Magnetic Tape Latency
"Geographic" (horribly high)
37
Magnetic Tape volatile
no
38
Magnetic Tape 2^k capacity
No
39
Magnetic Tape cost / bit
lowest non-volatile, cheapest overall
40
Magnetic Tape density
very high
41
Magnetic Tape location
"Where's Waldo??" (Doesn't matter)
42
Magnetic Tape controller complexity
complex
43
Order from most important aspect -> least important aspect
Latency,
Volatile,
2^k capacity,
cost / bit,
density,
location,
controller complexity
44
Speed
Latency
45
Does it lose data after being turned off?
Volatile
46
Does it save data after being turned off?
Non-volatile
47
locations can be accessed by dereferencing a pointer, and less complex controller
2^k capacity
48
How much money you have to spend
Cost / bit
49
total capacity for unit device, or capacity per unit area or per volume
Density
50
Where the memory is
Location
51
An interface to manage various incompatibilities between the processor and a physical memory device, translates pointers to addressing
Controller
CS 250
flashcards
Decks in class (12)
# Cards
