What is a shift register
A sequential logic circuit where a number of Flipflops are wired in such a way that data can be stored
What determines the number of bits that can be stored
The number of flipflops used
The number of flipflops used are equivalent to the number of bits that can be stored
What are four ways in which a shift register can be operated
SISO - Serial in Serial Out
SIPO - Serial in Parallel Out
PIPO - Parallel in Parallel Out
PISO - Parallel in Serial Out
Are shift registers ripple or synchronous
Synchronous they are all controlled by the same clock pulse
what are the main applications of shift registers
temporary storage, series to parallel and parallel to series conversion
digital delay circuit
mathematical operations
What can shift registers do to data?
store it, stop, copy and move or shift it to left or right, it can also convert the serial data to parallel data and vice versa
What is the most significant bit in the case of a shift register
the bit to be enters first
where is the most significant flip in any shift register
In PIPO its the highest numbered flipflop eg FF4 or the highest numbered output eg Q5
same goes for PISO but mainly its the first to be shifted out
in SISO its the furthest from the serial in
How many clock pulses does it take to load a Serial in shift register
The number of clock pulses to load a shift register is equivalent to the number of bits the register can store
How can a JK be wired to act as a D type FF
take a line from the input J but a not in that line and send it to K
How many clock pulses does it take to clear a fully loaded register
The number of clock pulses to clear a shift register is equivalent to the number of bits the register can store
What are 2 applications of a shift register ?
How does the Johnson shift counter operate
It is synchronous but does not count in true binary
The Q output of each Flipflop is high for 3 clock periods and low for 3 clock periods.
Since they are negative triggered and the output of the preceding stage is connected to the input of the preceding stage, the successive flip will only go high on the falling edge of the clock pulse that comes after the preceding flip flop went high
What’s another name for the Johnson shift counter
Twisted shift register
How does the Ring Shift Counter operate
It is synchronous but does not count in true binary
The Q output of each Flipflop is high for one clock period and low for 3 clock periods.
Since they are negative triggered and the output of the preceding stage is connected to the input of the preceding stage, the successive flip will only go high on the falling edge of the preceding flip flop
two 74194 as 8 bit
Qa 1 to dsl 2
and
Qd 2 dsr
SISO set up
set first jk as d type
Read line and load line for SIPO and PISO
load nand input and load line
read AND the read line and ouput
