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Question

Centr al pr ocessor unit (CPU)

Answer 1

Also called pr ocessor . The activ e par t of the computer , which contains the datapath and contr ol and which adds numbers, tests numbers, signals I/O de vices t o activ ate, and so on.

Answer 2

Also called pr ocessor . The activ e par t of the computer , which contains the datapath and contr ol and which adds numbers, tests numbers, signals I/O de vices t o activ ate, and so on. processor

Answer 3

Also called pr ocessor . The activ e par t of the computer , which contains the datapath and contr ol and which adds numbers, tests numbers, signals I/O de vices t o activ ate, and so on.

Answer 4

The component of the pr ocessor that per forms arithmetic oper ations.

Answer 5

The component of the pr ocessor that commands the datapath, memor y, and I/O de vices accor ding t o the instructions of the pr ogram.

Answer 6

The st orage ar ea in which pr ograms ar e kept when the y are running and that contains the data needed b y the running pr ograms.

Answer 7

Memor y built as an integr ated cir cuit; it pr ovides random access t o any location. Access times ar e 50 nanoseconds and cost per gigab yte in 2012 was $5 t o $10.

Answer 8

Memor y built as an integr ated cir cuit; it pr ovides random access t o any location. Access times ar e 50 nanoseconds and cost per gigab yte in 2012 was $5 t o $10.

Answer 9

A small, fast memor y that acts as a buff er for a slower , larger memor y.

Answer 10

Also memor y built as an integr ated cir cuit, but faster and less dense than DRAM.

Answer 11

Also called ar chitectur e. An abstr act inter face between the har dwar e and the lowest-le vel softwar e that encompasses all the information necessar y to write a machine language pr ogram that will run corr ectly , including instructions, r egisters, memor y access, I/O , and so on. architectur e

Answer 12

Also called ar chitectur e. An abstr act inter face between the har dwar e and the lowest-le vel softwar e that encompasses all the information necessar y to write a machine language pr ogram that will run corr ectly , including instructions, r egisters, memor y access, I/O , and so on.

Answer 13

The user por tion of the instruction set plus the oper ating system inter faces used b y application pr ogrammers. It denes a standar d for binar y por tability acr oss computers.

Answer 14

Har dwar e that obe ys the ar chitectur e abstr action.

Answer 15

St orage, such as DRAM, that r etains data only if it is r eceiving power .

Answer 16

A form of memor y that r etains data e ven in the absence of a power sour ce and that is used t o store programs between runs. A D VD disk is nonv olatile.

Answer 17

Also called primar y memor y. Memor y used t o hold pr ograms while the y are running; typically consists of DRAM in t oday's computers. primar y memor y

Answer 18

Also called primar y memor y. Memor y used t o hold pr ograms while the y are running; typically consists of DRAM in t oday's computers.

Answer 19

Nonv olatile memor y used t o store programs and data between runs; typically consists of ash memor y in PMDs and magnetic disks in ser vers.

Answer 20

Also called har d disk. A form of nonv olatile secondar y memor y composed of rotating platters coated with a magnetic r ecor ding material. Because the y are rotating mechanical devices, access times ar e about 5 t o 20 milliseconds and cost per gigab yte in 2012 was $0.05 t o $0.10.

Answer 21

A nonv olatile semiconduct or memor y. It is cheaper and slower than DRAM but more expensiv e per bit and faster than magnetic disks. Access times ar e about 5 t o 50 micr oseconds and cost per gigab yte in 2012 was $0.75 t o $1.00. networks Networks inter connect whole computers, allowing computer users t o extend the power of computing b y including communication.

Answer 22

A network designed t o carr y data within a geogr aphically conned ar ea, typically within a single building.

Answer 23

A network designed t o carr y data within a geogr aphically conned ar ea, typically within a single building.

Answer 24

A network extended o ver hundr eds of kilometers that can span a continent.

Answer 25

A network extended o ver hundr eds of kilometers that can span a continent. 2.5 Technologies for building pr ocessors and memor y

Answer 26

An on/off switch contr olled b y an electric signal.

Answer 27

A de vice containing hundr eds of thousands t o millions of transist ors.

Answer 28

A de vice containing hundr eds of thousands t o millions of transist ors.

Answer 29

A natur al element that is a semiconduct or.

Answer 30

A substance that does not conduct electricity well.

Answer 31

A r od composed of a silicon cr ystal that is between 8 and 12 inches in diameter and about 12 t o 24 inches long.

Answer 32

A slice fr om a silicon ingot no mor e than 0.1 inches thick, used t o create chips.

Answer 33

A micr oscopic aw in a waf er or in patterning steps that can r esult in the failur e of the die containing that def ect.

Answer 34

The individual r ectangular sections that ar e cut fr om a waf er, mor e informally known as chips. chips

Answer 35

The individual r ectangular sections that ar e cut fr om a waf er, mor e informally known as chips.

Answer 36

The per centage of good dies fr om the t otal number of dies on the waf er. 2.6 Performance

Answer 37

Also called ex ecution time. The t otal time r equir ed for the computer t o complete a task, including disk accesses, memor y accesses, I/O activities, oper ating system o verhead, CPU execution time, and so on. execution time

Answer 38

Also called ex ecution time. The t otal time r equir ed for the computer t o complete a task, including disk accesses, memor y accesses, I/O activities, oper ating system o verhead, CPU execution time, and so on.

Answer 39

Also called bandwidth. Another measur e of per formance, it is the number of tasks completed per unit time. bandwidth

Answer 40

Also called bandwidth. Another measur e of per formance, it is the number of tasks completed per unit time.

Answer 41

the computer that per forms the same amount of work in the least time is the fastest. wall clock time The most str aightfor ward denition of time is called wall clock time, r esponse time, or elapsed time. These terms mean the t otal time t o complete a task, including disk accesses, memor y accesses, input/output (I/O) activities, oper ating system o verhead—e verything. response time The most str aightfor ward denition of time is called wall clock time, r esponse time, or elapsed time. These terms mean the t otal time t o complete a task, including disk accesses, memor y accesses, input/output (I/O) activities, oper ating system o verhead—e verything. elapsed time The most str aightfor ward denition of time is called wall clock time, r esponse time, or elapsed time. These terms mean the t otal time t o complete a task, including disk accesses, memor y accesses, input/output (I/O) activities, oper ating system o verhead—e verything.

Answer 42

Also called CPU time. The actual time the CPU spends computing for a specic task.

Answer 43

Also called CPU time. The actual time the CPU spends computing for a specic task.

Answer 44

The CPU time spent in a pr ogram itself.

Answer 45

The CPU time spent in the oper ating system per forming tasks on behalf of the program. system per formance We will use the term system per formance t o refer to elapsed time on an unloaded system and CPU per formance t o refer to user CPU time. CPU per formance We will use the term system per formance t o refer to elapsed time on an unloaded system and CPU per formance t o refer to user CPU time. Clock r ate Clock r ate is the inv erse of the clock period.

Answer 46

Also called tick, clock tick, clock period, clock, or cy cle. The time for one clock period, usually of the pr ocessor clock, which runs at a constant r ate.

Answer 47

The length of each clock cy cle.

Answer 48

A verage number of clock cy cles per instruction for a pr ogram or program fr agment.

Answer 49

The number of instructions ex ecuted b y the pr ogram.

Answer 50

A measur e of the dynamic fr equency of instructions acr oss one or many programs. IPC Some designers inv ert CPI t o talk about IPC, or instructions per clock cy cle. If a pr ocessor executes on a verage two instructions per clock cy cle, then it has an IPC of 2 and hence a CPI of 0.5. instructions per clock cy cle Some designers inv ert CPI t o talk about IPC, or instructions per clock cy cle. If a pr ocessor executes on a verage two instructions per clock cy cle, then it has an IPC of 2 and hence a CPI of 0.5. 2.7 The power wall fanout The number of tr ansist ors connected t o an output (called the fanout). 2.8 The sea change: The switch fr om unipr ocessors t o multipr ocessors Redundant Arr ays of Inexpensiv e Disks Many disks in conjunction can off er much higher thr oughput, which was the original inspir ation of Redundant Arr ays of Inexpensiv e Disks (RAID). RAID Many disks in conjunction can off er much higher thr oughput, which was the original inspir ation of Redundant Arr ays of Inexpensiv e Disks (RAID). graphics pr ocessing unit The gr aphics pr ocessing unit (GPU) is a har dwar e component that acceler ates gr aphics. GPU The gr aphics pr ocessing unit (GPU) is a har dwar e component that acceler ates gr aphics. 2.9 Real stuff: Benchmarking the Intel Cor e i7

Answer 51

A set of pr ograms run on a computer that is either the actual collection of applications run b y a user or constructed fr om r eal pr ograms t o appr oximate such a mix. A typical workload species both the pr ograms and the r elativ e frequencies.

Answer 52

A pr ogram selected for use in comparing computer per formance. SPEC SPEC (System P erformance E valuation Cooper ative) is an effor t funded and suppor ted b y a number of computer v endors t o create standar d sets of benchmarks for modern computer systems. System P erformance E valuation Cooper ative SPEC (System P erformance E valuation Cooper ative) is an effor t funded and suppor ted b y a number of computer v endors t o create standar d sets of benchmarks for modern computer systems. SPECr atio Dividing the ex ecution time of a r eference pr ocessor b y the ex ecution time of the e valuated computer normaliz es the ex ecution time measur ements; this normalization yields a measur e, called the SPECr atio, which has the adv antage that bigger numeric r esults indicate faster performance. 2.10 Fallacies and pitfalls Amdahl' s Law Amdahl' s Law: A rule stating that the per formance enhancement possible with a giv en impr ovement is limited b y the amount that the impr oved featur e is used. It is a quantitativ e version of the law of diminishing r eturns.

Answer 53

A measur ement of pr ogram ex ecution speed based on the number of millions of instructions. MIPS is computed as the instruction count divided b y the product of the ex ecution time and 10 . 2.12 Historical perspectiv e and r eading J. Pr esper E ckert J. Pr esper E ckert and John Mauchly at the Moor e School of the Univ ersity of P ennsylv ania built what is widely accepted t o be the world' s rst oper ational electr onic, gener al-purpose computer called the ENI AC (Electr onic Numerical Integr ator and Calculat or). John Mauchly J. Pr esper E ckert and John Mauchly at the Moor e School of the Univ ersity of P ennsylv ania built what is widely accepted t o be the world' s rst oper ational electr onic, gener al-purpose computer called the ENI AC (Electr onic Numerical Integr ator and Calculat or). ENIAC J. Pr esper E ckert and John Mauchly at the Moor e School of the Univ ersity of P ennsylv ania built what is widely accepted t o be the world' s rst oper ational electr onic, gener al-purpose computer called the ENI AC (Electr onic Numerical Integr ator and Calculat or). von Neumann Von Neumann helped cr ystalliz e the ideas and wr ote a memo pr oposing a st ored-pr ogram computer called ED VAC (Electr onic Discr ete V ariable A utomatic Computer). EDVAC Von Neumann helped cr ystalliz e the ideas and wr ote a memo pr oposing a st ored-pr ogram computer called ED VAC (Electr onic Discr ete V ariable A utomatic Computer). EDSA C Wilk es decided t o embark on a pr oject t o build a st ored-pr ogram computer named EDSA C (Electr onic Dela y Storage A utomatic Calculat or). EDSA C star ted working in 1949 and was the world' s rst full-scale, oper ational, st ored-pr ogram computer . Mark-I6 6 A small pr ototype called the Mark-I, built at the Univ ersity of Manchester in 1948, might be called the rst oper ational st ored-pr ogram machine. John A tanasoff John A tanasoff, who built a small-scale electr onic computer in the early 1940s. Konrad Z use Another pioneering computer that deser ves cr edit was a special-purpose machine built b y Konrad Zuse in Germany in the late 1930s and early 1940s. Alan T uring During W orld W ar II special-purpose electr onic computers wer e built t o decr ypt inter cepted German messages. A team at Bletchle y Park, including Alan T uring, built the Colossus in 1943. Colossus During W orld W ar II special-purpose electr onic computers wer e built t o decr ypt inter cepted German messages. A team at Bletchle y Park, including Alan T uring, built the Colossus in 1943. Howar d Aik en Howar d Aik en was building an electr o-mechanical computer called the Mark-I at Har vard (a name that Manchester later adopted for its machine). Mark-I Howar d Aik en was building an electr o-mechanical computer called the Mark-I at Har vard (a name that Manchester later adopted for its machine). Harvard architectur e The term Har vard architectur e was coined t o describe machines with distinct memories. Whirlwind pr oject The Whirlwind pr oject was begun at MI T in 1947 and was aimed at applications in r eal-time r adar signal pr ocessing. Although it led t o several inv entions, its most impor tant inno vation was magnetic cor e memor y. BINAC Eckert and Mauchly formed E ckert-Mauchly Computer Corpor ation. Their rst machine, the BIN AC, was built for Nor throp and was shown in A ugust 1949. UNIV AC I Originally deliv ered in June 1951, UNIV AC I sold for about $1 million and was the rst successful commer cial computer . IBM 701 The rst IBM computer , the IBM 701, shipped in 1952, and e ventually 19 units wer e sold. Digital E quipment Corpor ation Digital E quipment Corpor ation (DEC ) unv eiled the PDP-8, the rst commer cial minicomputer . DEC Digital E quipment Corpor ation (DEC ) unv eiled the PDP-8, the rst commer cial minicomputer . PDP-8 Digital E quipment Corpor ation (DEC ) unv eiled the PDP-8, the rst commer cial minicomputer . minicomputer The minicomputer was a small machine that was a br eakthr ough in low-cost design, allowing DEC to off er a computer for under $20,000. Intel 4004 Intel inv enting the rst micr oprocessor in 1971—the Intel 4004. super computer Super computer , an extr emely fast computer tar geted t o per form a lar ge number of computations typically needed b y scientic applications. Seymour Cr ay Seymour Cr ay is often cr edited as the "father of super computing" and r egar ded as a pioneer of super computing. Cray-1 The Cr ay-1 was simultaneously the fastest in the world, the most expensiv e, and the computer with the best cost/per formance for scientic pr ograms. Apple IIe In 1977, the Apple IIe ( gur e below) fr om Ste ve Jobs and Ste ve Wozniak set standar ds for low cost, high v olume, and high r eliability that dened the personal computer industr y. Steve Jobs In 1977, the Apple IIe ( gur e below) fr om Ste ve Jobs and Ste ve Wozniak set standar ds for low cost, high v olume, and high r eliability that dened the personal computer industr y. Steve Wozniak In 1977, the Apple IIe ( gur e below) fr om Ste ve Jobs and Ste ve Wozniak set standar ds for low cost, high v olume, and high r eliability that dened the personal computer industr y. Xerox Alt o The computer that inspir ed many of the ar chitectur al and softwar e concepts that char acteriz e the modern deskt op machines was the X erox Alt o. ARPAnet The wide ar ea ARP Anet pr oduced the rst v ersions of Internet-style networking. Whetst one The Whetst one synthetic pr ogram was cr eated b y measuring scientic pr ograms written in Algol- 60. Dhrystone Dhrystone is another synthetic benchmark that is still used in some embedded computing cir cles. Kernels Kernels ar e small, time-intensiv e pieces fr om r eal pr ograms that ar e extr acted and then used as benchmarks. Livermor e Loops Livermor e Loops and Linpack ar e the best-known examples of k ernel benchmarks. Linpack Livermor e Loops and Linpack ar e the best-known examples of k ernel benchmarks. SPEC SPEC pr ovided benchmark sets for gr aphics, high-per formance scientic computing, object- oriented computing, le systems, W eb ser vers and clients, Ja va, engineering CAD applications, and power . Embedded Micr oprocessor Benchmark Consor tium The embedded community was inspir ed b y SPEC t o create the Embedded Micr oprocessor Benchmark Consor tium (EEMBC ). Star ted in 1997, it consists of a collection of k ernels or ganiz ed into suites that addr ess diff erent por tions of the embedded industr y. EEMBC The embedded community was inspir ed b y SPEC t o create the Embedded Micr oprocessor Benchmark Consor tium (EEMBC ). Star ted in 1997, it consists of a collection of k ernels or ganiz ed into suites that addr ess diff erent por tions of the embedded industr y. 3. Instructions 3.1 Introduction

Answer 54

The v ocabular y of commands underst ood b y a giv en ar chitectur e.

Answer 55

The idea that instructions and data of many types can be st ored in memor y as numbers and thus be easy t o change, leading t o the st ored-pr ogram computer . 3.2 Oper ations of the computer har dwar e comments The wor ds to the right of the double slashes (/ /) on each line ar e comments for the human r eader , so the computer ignor es them. 3.3 Oper ands of the computer har dwar e

Answer 56

A natur al unit of access in a computer , usually a gr oup of 32 bits.

Answer 57

Another natur al unit of access in a computer , usually a gr oup of 64 bits; corr esponds to the siz e of a r egister in the LEGv8 ar chitectur e.

Answer 58

A command that mo ves data between memor y and r egisters.

Answer 59

A v alue used t o delineate the location of a specic data element within a memor y arr ay. load The data tr ansf er instruction that copies data fr om memor y to a r egister is tr aditionally called load. base addr ess A base addr ess is the star ting addr ess of an arr ay in memor y. base r egister A base r egister is a r egister that holds an arr ay's base addr ess. offset An offset is a constant v alue added t o a base addr ess t o locate a par ticular arr ay element. spilling r egisters The pr ocess of putting less fr equently used v ariables (or those needed later) int o memor y is called spilling r egisters. 3.4 Signed and unsigned numbers

Answer 60

Also called binar y bit. One of the two numbers in base 2, 0 or 1, that ar e the components of information. Least signicant bit Least signicant bit: The rightmost bit in an LEGv8 doublewor d. Most signicant bit Most signicant bit: The leftmost bit in an LEGv8 doublewor d.. overow If the number that is the pr oper r esult of such oper ations cannot be r epresented b y these rightmost har dwar e bits, o verow is said t o ha ve occurr ed. sign and magnitude r epresentation Sign and magnitude r epresentation is a signed number r epresentation wher e a single bit is used t o represent the sign, and the r emaining bits r epresent the the magnitude. Two's complement Two's complement: A signed number r epresentation wher e a leading 0 indicates a positiv e number and a leading 1 indicates a negativ e number . The complement of a v alue is obtained b y complementing each bit (0 → 1 or 1 → 0), and then adding one t o the r esult. sign extension The function of a signed load is t o cop y the sign r epeatedly t o ll the r est of the r egister , known as a sign extension. One's complement One's complement: A notation that r epresents the most negativ e value b y 10 … 000 and the most positiv e value b y 01 … 11 , leaving an equal number of negativ es and positiv es but ending up with two z eros, one positiv e (00 … 00 ) and one negativ e (11 … 11 ). The term is also used to mean the inv ersion of e very bit in a pattern: 0 t o 1 and 1 t o 0.

Answer 61

A notation that r epresents the most negativ e value b y 00 … 000 and the most positiv e value b y 11 … 11 , with 0 typically ha ving the v alue 10 … 00 , ther eby biasing the number such that the number plus the bias has a non-negativ e representation. 3.5 Repr esenting instructions in the computer elds A machine instruction is composed of elds, each eld ha ving se veral bits and r epresenting some part of the instruction.two two two two two two two

Answer 62

A form of r epresentation of an instruction composed of elds of binar y numbers.

Answer 63

Binar y representation used for communication within a computer system.

Answer 64

Numbers in base 16.

Answer 65

The eld that denotes the oper ation and format of an instruction. destination r egister A destination r egister is a r egister that r eceiv es the r esult of an oper ation. 3.6 Logical oper ations shift A shift mo ves all the bits in a doublewor d to the left or right, lling the emptied bits with 0s.

Answer 66

A logical bit- b y-bit oper ation with two oper ands that calculates a 1 only if ther e is a 1 in both oper ands. mask AND can apply a bit pattern t o a set of bits t o for ce 0s wher e ther e is a 0 in the bit pattern. Such a bit pattern in conjunction with AND is tr aditionally called a mask, since the mask " conceals" some bits.

Answer 67

A logical bit-b y-bit oper ation with two oper ands that calculates a 1 if ther e is a 1 in either oper and.

Answer 68

A logical bit-b y-bit oper ation with one oper and that inv erts the bits; that is, it r eplaces e very 1 with a 0, and e very 0 with a 1.

Answer 69

A logical bit-b y-bit oper ation with two oper ands that calculates the ex clusiv e OR of the two oper ands. That is, it calculates a 1 only if the v alues ar e diff erent in the two oper ands. 3.7 Instructions for making decisions

Answer 70

An instruction that tests a v alue and that allows for a subsequent tr ansf er of contr ol to a new addr ess in the pr ogram based on the outcome of the test.

Answer 71

A sequence of instructions without br anches (ex cept possibly at the end) and without branch tar gets or br anch labels (ex cept possibly at the beginning).

Answer 72

Also called br anch table. A table of addr esses of alternativ e instruction sequences. branch table

Answer 73

Also called br anch table. A table of addr esses of alternativ e instruction sequences. 3.8 Suppor ting pr ocedur es in computer har dwar e

Answer 74

A st ored subr outine that per forms a specic task based on the par ameters with which it is pr ovided.

Answer 75

An instruction that br anches t o an addr ess and simultaneously sa ves the addr ess of the following instruction in a r egister (LR or X30 in LEGv8).

Answer 76

A link t o the calling site that allows a pr ocedur e to return t o the pr oper addr ess; in LEGv8 it is st ored in r egister LR (X30) .

Answer 77

The pr ogram that instigates a pr ocedur e and pr ovides the necessar y par ameter v alues.

Answer 78

A pr ocedur e that ex ecutes a series of st ored instructions based on par ameters pr ovided b y the caller and then r eturns contr ol to the caller .

Answer 79

The r egister containing the addr ess of the instruction in the pr ogram being executed. (PC)

Answer 80

The r egister containing the addr ess of the instruction in the pr ogram being executed.

Answer 81

A data structur e for spilling r egisters or ganiz ed as a last-in- rst-out queue.

Answer 82

A v alue denoting the most r ecently allocated addr ess in a stack that shows wher e registers should be spilled or wher e old r egister v alues can be found. In LEGv8, it is r egister SP.

Answer 83

Add element t o stack.

Answer 84

Remo ve element fr om stack.

Answer 85

The r egister that is r eser ved to point t o the static ar ea.

Answer 86

Also called activ ation r ecor d. The segment of the stack containing a pr ocedur e's saved registers and local v ariables. activ ation r ecor d

Answer 87

Also called activ ation r ecor d. The segment of the stack containing a pr ocedur e's saved registers and local v ariables.

Answer 88

A v alue denoting the location of the sa ved registers and local v ariables for a giv en procedur e.

Answer 89

The segment of a UNI X object le that contains the machine language code for routines in the sour ce le. 3.9 Communicating with people American Standar d Code for Information Inter change Most computers t oday off er 8-bit b ytes t o represent char acters, with the American Standar d Code for Information Inter change (ASCII) being the r epresentation that nearly e veryone follows. ASCII Most computers t oday off er 8-bit b ytes t o represent char acters, with the American Standar d Code for Information Inter change (ASCII) being the r epresentation that nearly e veryone follows. 3.10 LEGv8 addr essing for wide immediates and addr esses

Answer 90

An addr essing r egime in which the addr ess is the sum of the program counter (PC) and a constant in the instruction.

Answer 91

The oper and is a constant within the instruction itself.

Answer 92

The oper and is a r egister . Base addr essing / displacement addr essing Base addr essing / displacement addr essing: The oper and is at the memor y location whose addr ess is the sum of a r egister and a constant in the instruction.

Answer 93

The br anch addr ess is the sum of the PC and a constant in the instruction.

Answer 94

One of se veral addr essing r egimes delimited b y their v aried use of oper ands and/or addr esses. 3.11 Parallelism and instructions: synchr onization

Answer 95

T wo memor y accesses form a data r ace if the y are from diff erent thr eads t o same location, at least one is a write, and the y occur one after another . 3.12 Translating and star ting a pr ogram

Answer 96

A symbolic language that can be tr anslated int o binar y machine language.

Answer 97

A common v ariation of assembly language instructions often tr eated as if it were an instruction in its own right.

Answer 98

A table that matches names of labels t o the addr esses of the memor y wor ds that instructions occup y.

Answer 99

Also called link edit or. A systems pr ogram that combines independently assembled machine language pr ograms and r esolv es all undened labels int o an ex ecutable le. link edit or

Answer 100

Also called link edit or. A systems pr ogram that combines independently assembled machine language pr ograms and r esolv es all undened labels int o an ex ecutable le. Executable le Executable le: A functional pr ogram in the format of an object le that contains no unr esolv ed references. It can contain symbol tables and debugging information. A " stripped ex ecutable " does not contain that information. Relocation information ma y be included for the loader .

Answer 101

A systems pr ogram that places an object pr ogram in main memor y so that it is r eady t o execute.

Answer 102

Libr ary routines that ar e link ed to a pr ogram during ex ecution.

Answer 103

Libr ary routines that ar e link ed to a pr ogram during ex ecution.

Answer 104

Instruction fr om an instruction set designed t o interpr et Ja va programs.

Answer 105

The pr ogram that interpr ets Ja va bytecodes.

Answer 106

The pr ogram that interpr ets Ja va bytecodes.

Answer 107

The name commonly giv en to a compiler that oper ates at runtime, translating the interpr eted code segments int o the nativ e code of the computer .

Answer 108

The name commonly giv en to a compiler that oper ates at runtime, translating the interpr eted code segments int o the nativ e code of the computer . 3.15 Advanced material: Compiling C and interpr eting Ja va

Answer 109

A technique t o get mor e per formance fr om loops that access arr ays, in which multiple copies of the loop body ar e made and instructions fr om diff erent iter ations ar e scheduled together .

Answer 110

A Ja va keywor d that allows a method t o be inv oked b y any other method.

Answer 111

A Ja va keywor d that r estricts inv ocation of a method t o other methods in that package.

Answer 112

Basically a dir ectory that contains a gr oup of r elated classes.

Answer 113

A method that applies t o the whole class r ather t o an individual object. It is unrelated t o static in C. 3.18 Real stuff: x86 instructions

Answer 114

A r egister that can be used for addr esses or for data with vir tually any instruction.

Answer 115

A r egister that can be used for addr esses or for data with vir tually any instruction. 3.22 Historical perspectiv e and fur ther r eading

Answer 116

Ar chaic term for r egister . On-line use of it as a synonym for "r egister " is a fairly reliable indication that the user has been ar ound quite a while.

Answer 117

Also called r egister-r egister ar chitectur e. An instruction set ar chitectur e in which all oper ations ar e between r egisters and data memor y ma y only be accessed via loads or stores. register-r egister

Answer 118

Also called r egister-r egister ar chitectur e. An instruction set ar chitectur e in which all oper ations ar e between r egisters and data memor y ma y only be accessed via loads or stores. 4. Arithmetic for Computers 4.2 Addition and subtr action

Answer 119

Har dwar e that per forms addition, subtr action, and usually logical oper ations such as AND and OR.

Answer 120

Har dwar e that per forms addition, subtr action, and usually logical oper ations such as AND and OR. 4.4 Division

Answer 121

A number being divided.

Answer 122

A number that the dividend is divided b y.

Answer 123

The primar y result of a division; a number that when multiplied b y the divisor and added to the r emainder pr oduces the dividend.

Answer 124

The secondar y result of a division; a number that when added t o the pr oduct of the quotient and the divisor pr oduces the dividend. 4.5 Floating point Scientic notation Scientic notation: A notation that r enders numbers with a single digit t o the left of the decimal point.

Answer 125

A number in oating-point notation that has no leading 0s.

Answer 126

Computer arithmetic that r epresents numbers in which the binar y point is not x ed.

Answer 127

The v alue, gener ally between 0 and 1, placed in the fr action eld. The fr action is also called the mantissa .

Answer 128

In the numerical r epresentation system of oating-point arithmetic, the v alue that is placed in the exponent eld. Overow (oating-point) Overow (oating-point): A situation in which a positiv e exponent becomes t oo lar ge to t in the exponent eld. Underow (oating-point) Underow (oating-point): A situation in which a negativ e exponent becomes t oo lar ge to t in the exponent eld.

Answer 129

A oating-point v alue r epresented in a 64-bit doublewor d.

Answer 130

A oating-point v alue r epresented in a 32-bit wor d.

Answer 131

Also called interrupt. An unscheduled e vent that disrupts pr ogram ex ecution; used t o detect o verow . interrupt

Answer 132

Also called interrupt. An unscheduled e vent that disrupts pr ogram ex ecution; used t o detect o verow .

Answer 133

An ex ception that comes fr om outside of the pr ocesser . (Some ar chitectur es use the term interrupt for all ex ceptions. NaN IEEE 754 e ven has a symbol for the r esult of inv alid oper ations, such as 0/0 or subtr acting innity from innity . This symbol is NaN, for Not a Number . Not a Number IEEE 754 e ven has a symbol for the r esult of inv alid oper ations, such as 0/0 or subtr acting innity from innity . This symbol is NaN, for Not a Number .

Answer 134

The rst of two extr a bits k ept on the right during intermediate calculations of oating-point numbers; used t o impr ove rounding accur acy.

Answer 135

Method t o mak e the intermediate oating-point r esult t the oating-point format; the goal is typically t o nd the near est number that can be r epresented in the format. It is also the name of the second of two extr a bits k ept on the right during intermediate oating-point calculations, which impr oves rounding accur acy.

Answer 136

The number of bits in err or in the least signicant bits of the signicand between the actual number and the number that can be r epresented. ulp

Answer 137

The number of bits in err or in the least signicant bits of the signicand between the actual number and the number that can be r epresented.

Answer 138

A bit used in r ounding in addition t o guar d and r ound that is set whene ver ther e are nonz ero bits t o the right of the r ound bit.

Answer 139

A oating-point instruction that per forms both a multiply and an add, but rounds only once after the add. 4.12 Historical perspectiv e and fur ther r eading copr ocessor A copr ocessor is simply an additional chip that acceler ates a por tion of the work of a pr ocessor; in this case, it acceler ated oating-point computation. 5. The Pr ocessor 5.2 Logic design conv entions

Answer 140

An oper ational element, such as an AND gate or an AL U.

Answer 141

A memor y element, such as a r egister or a memor y.

Answer 142

The appr oach used t o determine when data is v alid and stable r elativ e to the clock.

Answer 143

A clocking scheme in which all state changes occur on a clock edge.

Answer 144

A signal used for multiplex or selection or for dir ecting the oper ation of a functional unit; contr asts with a data signal , which contains information that is oper ated on b y a functional unit.

Answer 145

The signal is logically high or true.

Answer 146

The signal is logically low or false. 5.3 Building a datapath

Answer 147

A unit used t o oper ate on or hold data within a pr ocessor . In the LEGv8 implementation, the datapath elements include the instruction and data memories, the r egister le, the AL U, and adders.

Answer 148

The r egister containing the addr ess of the instruction in the pr ogram being executed.

Answer 149

The r egister containing the addr ess of the instruction in the pr ogram being executed. Register le Register le: A state element that consists of a set of r egisters that can be r ead and written b y supplying a r egister number t o be accessed.

Answer 150

T o incr ease the siz e of a data item b y replicating the high-or der sign bit of the original data item in the high-or der bits of the lar ger, destination data item.

Answer 151

The addr ess specied in a br anch, which becomes the new pr ogram counter (PC ) if the br anch is tak en. In the LEGv8 ar chitectur e, the br anch tar get is giv en b y the sum of the offset eld of the instruction and the addr ess of the br anch.

Answer 152

A br anch wher e the br anch condition is satised and the pr ogram counter (PC ) becomes the br anch tar get. All unconditional br anches ar e tak en br anches.

Answer 153

A br anch wher e the br anch condition is false and the program counter (PC ) becomes the addr ess of the instruction that sequentially follows the br anch. untak en br anch

Answer 154

A br anch wher e the br anch condition is false and the program counter (PC ) becomes the addr ess of the instruction that sequentially follows the br anch. 5.4 A simple implementation scheme

Answer 155

F rom logic, a r epresentation of a logical oper ation b y listing all the v alues of the inputs and then in each case showing what the r esulting outputs should be. Don't-car e term Don't-car e term: An element of a logical function in which the output does not depend on the values of all the inputs. Don 't-car e terms ma y be specied in diff erent wa ys.

Answer 156

The eld that denotes the oper ation and format of an instruction.

Answer 157

Also called single clock cy cle implementation. An implementation in which an instruction is ex ecuted in one clock cy cle. While easy t o understand, it is t oo slow t o be practical. single clock cy cle implementation

Answer 158

Also called single clock cy cle implementation. An implementation in which an instruction is ex ecuted in one clock cy cle. While easy t o understand, it is t oo slow t o be practical. 5.5 An o verview of pipelining

Answer 159

An implementation technique in which multiple instructions ar e overlapped in execution, much lik e an assembly line.

Answer 160

When a planned instruction cannot ex ecute in the pr oper clock cy cle because the har dwar e does not suppor t the combination of instructions that ar e set t o execute.

Answer 161

Also called a pipeline data hazar d. When a planned instruction cannot ex ecute in the proper clock cy cle because data that is needed t o execute the instruction ar e not y et available. pipeline data hazar d

Answer 162

Also called a pipeline data hazar d. When a planned instruction cannot ex ecute in the proper clock cy cle because data that is needed t o execute the instruction ar e not y et available.

Answer 163

Also called b ypassing. A method of r esolving a data hazar d by retrie ving the missing data element fr om internal buff ers r ather than waiting for it t o arriv e from pr ogrammer-visible registers or memor y. bypassing

Answer 164

Also called b ypassing. A method of r esolving a data hazar d by retrie ving the missing data element fr om internal buff ers r ather than waiting for it t o arriv e from pr ogrammer-visible registers or memor y.

Answer 165

A specic form of data hazar d in which the data being loaded b y a load instruction has not y et become a vailable when it is needed b y another instruction.

Answer 166

Also called bubble. A stall initiated in or der t o resolv e a hazar d. bubble

Answer 167

Also called bubble. A stall initiated in or der t o resolv e a hazar d.

Answer 168

Also called br anch hazar d. When the pr oper instruction cannot ex ecute in the proper pipeline clock cy cle because the instruction that was f etched is not the one that is needed; that is, the ow of instruction addr esses is not what the pipeline expected. branch hazar d

Answer 169

Also called br anch hazar d. When the pr oper instruction cannot ex ecute in the proper pipeline clock cy cle because the instruction that was f etched is not the one that is needed; that is, the ow of instruction addr esses is not what the pipeline expected.

Answer 170

A method of r esolving a br anch hazar d that assumes a giv en outcome for the conditional br anch and pr oceeds fr om that assumption r ather than waiting t o ascer tain the actual outcome.

Answer 171

The number of stages in a pipeline or the number of stages between two instructions during ex ecution. pipeline

Answer 172

The number of stages in a pipeline or the number of stages between two instructions during ex ecution. 5.7 Data hazar ds: F orwarding v ersus stalling nop

Answer 173

An instruction that does no oper ation t o change state. 5.8 Contr ol hazar ds

Answer 174

T o discar d instructions in a pipeline, usually due t o an unexpected e vent.

Answer 175

Pr ediction of br anches at runtime using runtime information.

Answer 176

Also called br anch hist ory table. A small memor y that is index ed b y the lower por tion of the addr ess of the br anch instruction and that contains one or mor e bits indicating whether the br anch was r ecently tak en or not. branch hist ory table

Answer 177

Also called br anch hist ory table. A small memor y that is index ed b y the lower por tion of the addr ess of the br anch instruction and that contains one or mor e bits indicating whether the br anch was r ecently tak en or not.

Answer 178

A structur e that caches the destination PC or destination instruction for a branch. It is usually or ganiz ed as a cache with tags, making it mor e costly than a simple pr ediction buffer.

Answer 179

A br anch pr edict or that combines local beha vior of a par ticular br anch and global information about the beha vior of some r ecent number of ex ecuted br anches.

Answer 180

A br anch pr edict or with multiple pr edictions for each br anch and a selection mechanism that chooses which pr edict or to enable for a giv en br anch. 5.9 Exceptions

Answer 181

Also called interrupt. An unscheduled e vent that disrupts pr ogram ex ecution; used t o detect o verow . interrupt

Answer 182

Also called interrupt. An unscheduled e vent that disrupts pr ogram ex ecution; used t o detect o verow .

Answer 183

An ex ception that comes fr om outside of the pr ocessor . (Some ar chitectur es use the term interrupt for all ex ceptions.).

Answer 184

An interrupt for which the addr ess t o which contr ol is tr ansf erred is determined by the cause of the ex ception.

Answer 185

Also called impr ecise ex ception. Interrupts or ex ceptions in pipelined computers that ar e not associated with the exact instruction that was the cause of the interrupt or exception. impr ecise ex ception

Answer 186

Also called impr ecise ex ception. Interrupts or ex ceptions in pipelined computers that ar e not associated with the exact instruction that was the cause of the interrupt or exception.

Answer 187

Also called pr ecise ex ception. An interrupt or ex ception that is alwa ys associated with the corr ect instruction in pipelined computers. precise ex ception

Answer 188

Also called pr ecise ex ception. An interrupt or ex ception that is alwa ys associated with the corr ect instruction in pipelined computers. 5.10 Parallelism via instructions

Answer 189

The par allelism among instructions.

Answer 190

A scheme wher eby multiple instructions ar e launched in one clock cy cle.

Answer 191

An appr oach t o implementing a multiple-issue pr ocessor wher e many decisions ar e made b y the compiler befor e execution.

Answer 192

An appr oach t o implementing a multiple-issue pr ocessor wher e many decisions ar e made during ex ecution b y the pr ocessor .

Answer 193

The positions fr om which instructions could issue in a giv en clock cy cle; b y analogy , these corr espond t o positions at the star ting blocks for a sprint.

Answer 194

An appr oach wher eby the compiler or pr ocessor guesses the outcome of an instruction t o remo ve it as a dependence in ex ecuting other instructions.

Answer 195

The set of instructions that issues t ogether in one clock cy cle; the pack et ma y be determined statically b y the compiler or dynamically b y the pr ocessor .

Answer 196

A style of instruction set ar chitectur e that launches many oper ations that ar e dened t o be independent in a single wide instruction, typically with many separ ate opcode elds.

Answer 197

A style of instruction set ar chitectur e that launches many oper ations that ar e dened t o be independent in a single wide instruction, typically with many separ ate opcode elds.

Answer 198

Number of clock cy cles between a load instruction and an instruction that can use the r esult of the load without stalling the pipeline.

Answer 199

A technique t o get mor e per formance fr om loops that access arr ays, in which multiple copies of the loop body ar e made and instructions fr om diff erent iter ations ar e scheduled together .

Answer 200

The r enaming of r egisters b y the compiler or har dwar e to remo ve antidependences.

Answer 201

Also called name dependence. An or dering for ced b y the r euse of a name, typically a r egister , rather than b y a true dependence that carries a v alue between two instructions. name dependence

Answer 202

Also called name dependence. An or dering for ced b y the r euse of a name, typically a r egister , rather than b y a true dependence that carries a v alue between two instructions.

Answer 203

An adv anced pipelining technique that enables the pr ocessor t o execute mor e than one instruction per clock cy cle b y selecting them during ex ecution.

Answer 204

Har dwar e suppor t for r eordering the or der of instruction ex ecution t o avoid stalls.

Answer 205

The unit in a dynamic or out-of-or der ex ecution pipeline that decides when it is saf e to release the r esult of an oper ation t o programmer-visible r egisters and memor y.

Answer 206

A buff er within a functional unit that holds the oper ands and the oper ation.

Answer 207

The buff er that holds r esults in a dynamically scheduled pr ocessor until it is saf e to store the r esults t o memor y or a r egister .

Answer 208

A situation in pipelined ex ecution when an instruction block ed fr om executing does not cause the following instructions t o wait.

Answer 209

A commit in which the r esults of pipelined ex ecution ar e written t o the programmer visible state in the same or der that instructions ar e fetched. 5.11 Real stuff: The ARM Cor tex-A53 and Intel Cor e i7 pipelines

Answer 210

The or ganization of the pr ocessor , including the major functional units, their inter connection, and contr ol.

Answer 211

The instruction set of visible r egisters of a pr ocessor; for example, in LEGv8, these ar e the 32 integer and 32 oating-point r egisters. 5.15 Concluding r emarks

Answer 212

The inher ent ex ecution time for an instruction. 6. Memor y Hier archy 6.1 Introduction

Answer 213

The locality principle stating that if a data location is r eferenced then it will tend to be r eferenced again soon.

Answer 214

The locality principle stating that if a data location is r eferenced, data locations with nearb y addr esses will tend t o be r eferenced soon.

Answer 215

A structur e that uses multiple le vels of memories; as the distance fr om the processor incr eases, the siz e of the memories and the access time both incr ease.

Answer 216

The minimum unit of information that can be either pr esent or not pr esent in a cache.

Answer 217

The fr action of memor y accesses found in a le vel of the memor y hier archy.

Answer 218

The fr action of memor y accesses not found in a le vel of the memor y hier archy.

Answer 219

The time r equir ed to access a le vel of the memor y hier archy, including the time needed t o determine whether the access is a hit or a miss.

Answer 220

The time r equir ed to fetch a block int o a le vel of the memor y hier archy fr om the lower le vel, including the time t o access the block, tr ansmit it fr om one le vel to the other , inser t it in the le vel that experienced the miss, and then pass the block t o the r equest or. 6.2 Memor y technologies Flash memor y Flash memor y is a type of electrically er asable pr ogrammable r ead-only memor y (EEPROM).

Answer 221

One of thousands of concentric cir cles that mak e up the sur face of a magnetic disk.

Answer 222

One of the segments that mak e up a tr ack on a magnetic disk; a sect or is the smallest amount of information that is r ead or written on a disk.

Answer 223

The pr ocess of positioning a r ead/write head o ver the pr oper tr ack on a disk.

Answer 224

Also called r otational dela y. The time r equir ed for the desir ed sect or of a disk t o rotate under the r ead/write head; usually assumed t o be half the r otation time. rotational dela y

Answer 225

Also called r otational dela y. The time r equir ed for the desir ed sect or of a disk t o rotate under the r ead/write head; usually assumed t o be half the r otation time. 6.3 The basics of caches

Answer 226

A cache structur e in which each memor y location is mapped t o exactly one location in the cache.

Answer 227

A eld in a table used for a memor y hier archy that contains the addr ess information r equir ed to identify whether the associated block in the hier archy corr esponds t o a r equested wor d.

Answer 228

A eld in the tables of a memor y hier archy that indicates that the associated block in the hierarchy contains v alid data.

Answer 229

A r equest for data fr om the cache that cannot be lled because the data ar e not present in the cache.

Answer 230

A scheme in which writes alwa ys update both the cache and the next lower le vel of the memor y hier archy, ensuring that data ar e alwa ys consistent between the two.

Answer 231

A queue that holds data while the data ar e waiting t o be written t o memor y.

Answer 232

A scheme that handles writes b y updating v alues only t o the block in the cache, then writing the modied block t o the lower le vel of the hier archy when the block is r eplaced.

Answer 233

A scheme in which a le vel of the memor y hier archy is composed of two independent caches that oper ate in par allel with each other , with one handling instructions and one handling data. 6.4 Measuring and impr oving cache per formance

Answer 234

A cache structur e in which a block can be placed in any location in the cache.

Answer 235

A cache that has a x ed number of locations (at least two) wher e each block can be placed.

Answer 236

A r eplacement scheme in which the block r eplaced is the one that has been unused for the longest time.

Answer 237

A r eplacement scheme in which the block r eplaced is the one that has been unused for the longest time.

Answer 238

A memor y hier archy with multiple le vels of caches, r ather than just a cache and main memor y.

Answer 239

The fr action of r eferences that miss in all le vels of a mutlile vel cache.

Answer 240

The fr action of r eferences t o one le vel of a cache that miss; used in multile vel hierarchies. 6.5 Dependable memor y hier archy

Answer 241

A code that enables the detection of an err or in data, but not the pr ecise location and, hence, corr ection of the err or. 6.7 Virtual memor y

Answer 242

A technique that uses main memor y as a " cache " for secondar y storage.

Answer 243

An addr ess in main memor y.

Answer 244

A set of mechanisms for ensuring that multiple pr ocesses sharing the pr ocessor , memor y, or I/O de vices cannot inter fere, intentionally or unintentionally , with one another b y reading or writing each other 's data. These mechanisms also isolate the oper ating system fr om a user pr ocess.

Answer 245

An e vent that occurs when an accessed page is not pr esent in main memor y.

Answer 246

An addr ess that corr esponds t o a location in vir tual space and is tr anslated b y addr ess mapping t o a physical addr ess when memor y is accessed.

Answer 247

Also called addr ess mapping. The pr ocess b y which a vir tual addr ess is mapped t o an addr ess used t o access memor y. addr ess mapping

Answer 248

Also called addr ess mapping. The pr ocess b y which a vir tual addr ess is mapped t o an addr ess used t o access memor y.

Answer 249

A v ariable-siz e addr ess mapping scheme in which an addr ess consists of two parts: a segment number , which is mapped t o a physical addr ess, and a segment offset.

Answer 250

The table containing the vir tual t o physical addr ess tr anslations in a vir tual memor y system. The table, which is st ored in memor y, is typically index ed b y the vir tual page number; each entry in the table contains the physical page number for that vir tual page if the page is curr ently in memor y.

Answer 251

The space on the disk r eser ved for the full vir tual memor y space of a pr ocess.

Answer 252

Also called use bit or access bit. A eld that is set whene ver a page is accessed and that is used t o implement LRU or other r eplacement schemes. use bit

Answer 253

Also called use bit or access bit. A eld that is set whene ver a page is accessed and that is used t o implement LRU or other r eplacement schemes. access bit

Answer 254

Also called use bit or access bit. A eld that is set whene ver a page is accessed and that is used t o implement LRU or other r eplacement schemes.

Answer 255

A cache that k eeps tr ack of r ecently used addr ess mappings t o try to avoid an access t o the page table.

Answer 256

A cache that is accessed with a vir tual addr ess r ather than a physical addr ess.

Answer 257

A situation in which two addr esses access the same object; it can occur in vir tual memor y when ther e are two vir tual addr esses for the same physical page.

Answer 258

A cache that is addr essed b y a physical addr ess.

Answer 259

Also called k ernal mode. A mode indicating that a running pr ocess is an oper ating system pr ocess. kernal mode

Answer 260

Also called k ernal mode. A mode indicating that a running pr ocess is an oper ating system pr ocess.

Answer 261

A special instruction that tr ansf ers contr ol from user mode t o a dedicated location in super visor code space, inv oking the ex ception mechanism in the pr ocess.

Answer 262

A changing of the internal state of the pr ocessor t o allow a diff erent pr ocess t o use the pr ocessor that includes sa ving the state needed t o return t o the curr ently ex ecuting process.

Answer 263

Also called interrupt enable. A signal or action that contr ols whether the pr ocess responds t o an ex ception or not; necessar y for pr eventing the occurr ence of ex ceptions during inter vals befor e the pr ocessor has saf ely sa ved the state needed t o restar t.

Answer 264

An instruction that can r esume ex ecution after an ex ception is r esolv ed without the ex ception 's aff ecting the r esult of the instruction. 6.8 A common fr amework for memor y hier archy

Answer 265

A cache model in which all cache misses ar e classied int o one of thr ee categories: compulsor y misses, capacity misses, and conict misses.

Answer 266

Also called cold-star t miss. A cache miss caused b y the rst access t o a block that has ne ver been in the cache. cold-star t miss

Answer 267

Also called cold-star t miss. A cache miss caused b y the rst access t o a block that has ne ver been in the cache.

Answer 268

A cache miss that occurs because the cache, e ven with full associativity , cannot contain all the blocks needed t o satisfy the r equest. Conict miss Conict miss: Also called collision miss. A cache miss that occurs in a set-associativ e or dir ect- mapped cache when multiple blocks compete for the same set and that ar e eliminated in a fully associativ e cache of the same siz e. collision miss Conict miss: Also called collision miss. A cache miss that occurs in a set-associativ e or dir ect- mapped cache when multiple blocks compete for the same set and that ar e eliminated in a fully associativ e cache of the same siz e. 6.9 Using a nite-state machine t o contr ol a simple cache

Answer 269

A sequential logic function consisting of a set of inputs and outputs, a next- state function that maps the curr ent state and the inputs t o a new state, and an output function that maps the curr ent state and possibly the inputs t o a set of asser ted outputs.

Answer 270

A combinational function that, giv en the inputs and the curr ent state, determines the next state of a nite-state machine. 6.10 Parallelism and memor y hier archies: Cache coher ence

Answer 271

When two unr elated shar ed variables ar e located in the same cache block and the full block is ex changed between pr ocessors e ven though the pr ocessors ar e accessing diff erent variables. 6.11 Parallelism and memor y hier archy: Redundant arr ays of inexpensiv e disks

Answer 272

An or ganization of disks that uses an arr ay of small and inexpensiv e disks so as t o incr ease both per formance and r eliability .

Answer 273

An or ganization of disks that uses an arr ay of small and inexpensiv e disks so as t o incr ease both per formance and r eliability .

Answer 274

Allocation of logically sequential blocks t o separ ate disks t o allow higher per formance than a single disk can deliv er.

Answer 275

W riting identical data t o multiple disks t o incr ease data a vailability .

Answer 276

The gr oup of data disks or blocks that shar e a common check disk or block.

Answer 277

Replacing a har dwar e component while the system is running.

Answer 278

Reser ve har dwar e resour ces that can immediately tak e the place of a failed component. 6.13 Real stuff: The ARM Cor tex-A53 and Intel Cor e i7 memor y hier archies

Answer 279

A cache that allows the pr ocessor t o mak e references t o the cache while the cache is handling an earlier miss. 6.17 Concluding r emarks

Answer 280

A technique in which data blocks needed in the futur e are brought int o the cache early by using special instructions that specify the addr ess of the block. 7. Parallel Pr ocessors 7.1 Introduction mathematical model A mathematical model is an equation used t o represent data. variable A variable is a symbol r epresenting data. Ex: T is a common v ariable r epresenting temper ature. independent v ariable An independent v ariable is a symbol r epresenting an input. Ex: x is a common independent variable. A simple wa y to remember independent v ariables ar e for input is 'I' for independent and input.[c] . dependent v ariable A dependent v ariable is a symbol r epresenting an output. Ex: y is a common dependent v ariable. parameters Parameters ar e added and adjusted. Ex: Data modeled t o a line has two par ameters, m and b, such that y = m ∙ x + b. trendline A trendline is a model that captur es changes in data.

Answer 281

A computer system with at least two pr ocessors. This computer is in contr ast t o a unipr ocessor , which has one, and is incr easingly har d to nd t oday.

Answer 282

A single pr ogram that runs on multiple pr ocessors simultaneously .

Answer 283

A set of computers connected o ver a local ar ea network that function as a single lar ge multipr ocessor .

Answer 284

A micr oprocessor containing multiple pr ocessors (" cores") in a single integr ated cir cuit. Vir tually all micr oprocessors t oday in deskt ops and ser vers ar e multicor e.

Answer 285

A par allel pr ocessor with a single physical addr ess space.

Answer 286

A par allel pr ocessor with a single physical addr ess space. 7.2 The diculty of cr eating par allel pr ocessing pr ograms

Answer 287

Speed-up achie ved on a multipr ocessor without incr easing the siz e of the pr oblem.

Answer 288

Speed-up achie ved on a multipr ocessor while incr easing the siz e of the pr oblem propor tionally t o the incr ease in the number of pr ocessors. 7.3 SISD , MIMD , SIMD , SPMD , and v ector SISD SISD or single instruction str eam, single data str eam: A unipr ocessor . single instruction str eam SISD or single instruction str eam, single data str eam: A unipr ocessor . single data str eam SISD or single instruction str eam, single data str eam: A unipr ocessor . MIMD MIMD or multiple instruction str eams, multiple data str eams: A multipr ocessor . multiple instruction str eams MIMD or multiple instruction str eams, multiple data str eams: A multipr ocessor . multiple data str eams MIMD or multiple instruction str eams, multiple data str eams: A multipr ocessor . SPMD SPMD or single pr ogram, multiple data str eams: The conv entional MIMD pr ogramming model, wher e a single pr ogram runs acr oss all pr ocessors. single pr ogram, multiple data str eams SPMD or single pr ogram, multiple data str eams: The conv entional MIMD pr ogramming model, wher e a single pr ogram runs acr oss all pr ocessors. SIMD SIMD or single instruction str eam, multiple data str eams: The same instruction is applied t o many data str eams, as in a v ector pr ocessor . single instruction str eam, multiple data str eams SIMD or single instruction str eam, multiple data str eams: The same instruction is applied t o many data str eams, as in a v ector pr ocessor .

Answer 289

P arallelism achie ved b y per forming the same oper ation on independent data.

Answer 290

One or mor e vector functional units and a por tion of the v ector register le. Inspir ed b y lanes on highwa ys that incr ease tr ac speed, multiple lanes ex ecute v ector oper ations simultaneously . 7.4 Hardwar e multithr eading

Answer 291

Incr easing utilization of a pr ocessor b y switching t o another thr ead when one thr ead is stalled.

Answer 292

A thr ead includes the pr ogram counter , the r egister state, and the stack. It is a lightweight process; wher eas thr eads commonly shar e a single addr ess space, pr ocesses don 't.

Answer 293

A pr ocess includes one or mor e thr eads, the addr ess space, and the oper ating system state. Hence, a pr ocess switch usually inv okes the oper ating system, but not a thr ead switch.

Answer 294

A v ersion of har dwar e multithr eading that implies switching between threads after e very instruction.

Answer 295

A v ersion of har dwar e multithr eading that implies switching between thr eads only after signicant e vents, such as a last-le vel cache miss.

Answer 296

A v ersion of multithr eading that lowers the cost of multithr eading b y utilizing the r esour ces needed for multiple issue, dynamically scheduled micr oarchitectur e.

Answer 297

A v ersion of multithr eading that lowers the cost of multithr eading b y utilizing the r esour ces needed for multiple issue, dynamically scheduled micr oarchitectur e. 7.5 Multicor e and other shar ed memor y multipr ocessors

Answer 298

A multipr ocessor in which latency t o any wor d in main memor y is about the same no matter which pr ocessor r equests the access.

Answer 299

A multipr ocessor in which latency t o any wor d in main memor y is about the same no matter which pr ocessor r equests the access.

Answer 300

A type of single addr ess space multipr ocessor in which some memor y accesses ar e much faster than others depending on which pr ocessor asks for which wor d.

Answer 301

A type of single addr ess space multipr ocessor in which some memor y accesses ar e much faster than others depending on which pr ocessor asks for which wor d.

Answer 302

The pr ocess of coor dinating the beha vior of two or mor e processes, which ma y be running on diff erent pr ocessors.

Answer 303

A synchr onization de vice that allows access t o data t o only one pr ocessor at a time.

Answer 304

A function that pr ocesses a data structur e and r eturns a single v alue.

Answer 305

An API for shar ed memor y multipr ocessing in C, C++, or F ortran that runs on UNI X and Micr osoft platforms. It includes compiler dir ectiv es, a libr ary, and runtime dir ectiv es. 7.7 Clusters, war ehouse scale computers, and other message-passing multipr ocessors

Answer 306

Communicating between multiple pr ocessors b y explicitly sending and receiving information.

Answer 307

A r outine used b y a pr ocessor in machines with priv ate memories t o pass a message t o another pr ocessor .

Answer 308

A r outine used b y a pr ocessor in machines with priv ate memories t o accept a message fr om another pr ocessor .

Answer 309

Collections of computers connected via I/O o ver standar d network switches t o form a message-passing multipr ocessor .

Answer 310

Rather than selling softwar e that is installed and run on cust omers' own computers, softwar e is run at a r emote site and made a vailable o ver the Internet typically via a Web inter face t o cust omers. SaaS cust omers ar e char ged based on use v ersus on ownership.

Answer 311

Rather than selling softwar e that is installed and run on cust omers' own computers, softwar e is run at a r emote site and made a vailable o ver the Internet typically via a Web inter face t o cust omers. SaaS cust omers ar e char ged based on use v ersus on ownership. 7.8 Introduction t o multipr ocessor network t opologies

Answer 312

Informally , the peak tr ansf er rate of a network; can r efer to the speed of a single link or the collectiv e transf er rate of all links in the network.

Answer 313

The bandwidth between two equal par ts of a multipr ocessor . This measur e is for a worst case split of the multipr ocessor .

Answer 314

A network that connects pr ocessor-memor y nodes b y supplying a dedicated communication link between e very node.

Answer 315

A network that supplies a small switch at each node.

Answer 316

A network that allows any node t o communicate with any other node in one pass thr ough the network. 7.9 Communicating t o the outside world: Cluster networking Memor y-mapped I/O Memor y-mapped I/O: An I/O scheme in which por tions of the addr ess space ar e assigned t o I/O devices, and r eads and writes t o those addr esses ar e interpr eted as commands t o the I/O de vice.

Answer 317

A mechanism that pr ovides a de vice contr oller with the ability t o transf er data dir ectly t o or fr om the memor y without inv olving the pr ocessor .

Answer 318

A mechanism that pr ovides a de vice contr oller with the ability t o transf er data dir ectly t o or fr om the memor y without inv olving the pr ocessor . Interrupt-driv en I/O Interrupt-driv en I/O: An I/O scheme that emplo ys interrupts t o indicate t o the pr ocessor that an I/O device needs attention.

Answer 319

A pr ogram that contr ols an I/O de vice that is attached t o the computer .

Answer 320

The pr ocess of periodically checking the status of an I/O de vice t o determine the need t o service the de vice. 7.10 Multipr ocessor benchmarks and per formance models

Answer 321

A UNI X API for cr eating and manipulating thr eads. It is structur ed as a libr ary.

Answer 322

The r atio of oating-point oper ations in a pr ogram t o the number of data bytes accessed b y a pr ogram fr om main memor y. 8. Appendix A 8.2 Gates, truth tables, and logic equations

Answer 323

A signal that is (logically) true, or 1.

Answer 324

A signal that is (logically) false, or 0.

Answer 325

A logic system whose blocks do not contain memor y and hence compute the same output giv en the same input.

Answer 326

A gr oup of logic elements that contain memor y and hence whose v alue depends on the input as well as the curr ent contents of the memor y.

Answer 327

A de vice that implements basic logic functions, such as AND or OR. universal NOR and N AND gates ar e called univ ersal, since any logic function can be built using this one gate type.

Answer 328

An inv erted OR gate.

Answer 329

An inv erted AND gate. 8.3 Combinational logic encoder An encoder that per forms the inv erse function of a decoder , taking 2 inputs and pr oducing an n- bit output.

Answer 330

A logic block that has an n-bit input and 2 outputs, wher e only one output is asser ted for each input combination. multiplex or A multiplex or might mor e properly be called a select or, since its output is one of the inputs that is selected b y a contr ol. select or A multiplex or might mor e properly be called a select or, since its output is one of the inputs that is selected b y a contr ol.

Answer 331

Also called contr ol value. The contr ol signal that is used t o select on of the input values of a multiplex or as the output of the multiplex or. contr ol value

Answer 332

Also called contr ol value. The contr ol signal that is used t o select on of the input values of a multiplex or as the output of the multiplex or.

Answer 333

A form of logical r epresentation that emplo ys a logical sum (OR) of pr oducts (terms joined using the AND oper ator).

Answer 334

A structur ed-logic element composed of a set of inputs and corresponding input complements and two stages of logic: the rst gener ates pr oduct terms of the inputs and input complements, and the second gener ates sum terms of the pr oduct terms. Hence, PL As implement logic functions as a sum of pr oducts.

Answer 335

A structur ed-logic element composed of a set of inputs and corresponding input complements and two stages of logic: the rst gener ates pr oduct terms of the inputs and input complements, and the second gener ates sum terms of the pr oduct terms. Hence, PL As implement logic functions as a sum of pr oducts.

Answer 336

Also called pr oduct terms. A set of logic inputs joined b y conjunction (AND oper ations); the pr oduct terms form the rst logic stage of the programmable logic arr ay (PLA). product terms

Answer 337

Also called pr oduct terms. A set of logic inputs joined b y conjunction (AND oper ations); the pr oduct terms form the rst logic stage of the programmable logic arr ay (PLA).

Answer 338

A memor y whose contents ar e designated at cr eation time, after which the contents can only be r ead. ROM is used as structur ed logic t o implement a set of logic functions b y using the terms in the logic functions as addr ess inputs and the outputs as bits in each wor d of the memor y.

Answer 339

A memor y whose contents ar e designated at cr eation time, after which the contents can only be r ead. ROM is used as structur ed logic t o implement a set of logic functions b y using the terms in the logic functions as addr ess inputs and the outputs as bits in each wor d of the memor y.

Answer 340

A form of r ead-only memor y that can be pr ogrammed when a designer knows its contents.

Answer 341

A form of r ead-only memor y that can be pr ogrammed when a designer knows its contents.

Answer 342

In logic design, a collection of data lines that is tr eated t ogether as a single logical signal; also, a shar ed collection of lines with multiple sour ces and uses. 8.4 Using a har dwar e description language

Answer 343

A pr ogramming language for describing har dwar e, used for gener ating simulations of a har dwar e design and also as input t o synthesis t ools that can gener ate actual har dwar e.

Answer 344

One of the two most common har dwar e description languages.

Answer 345

One of the two most common har dwar e description languages. Beha vioral specication Beha vioral specication: Describes how a digital system oper ates functionally . Structur al specication Structur al specication: Describes how a digital system is or ganiz ed in terms of a hier archical connection of elements.

Answer 346

Computer-aided design softwar e that can gener ate a gate-le vel design based on beha vioral descriptions of a digital system.

Answer 347

In V erilog, species a combinational signal.

Answer 348

In V erilog, a r egister .

Answer 349

The list of signals that species when an always block should be r e-evaluated.

Answer 350

In V erilog, an assignment that completes befor e the ex ecution of the next statement.

Answer 351

An assignment that continues after e valuating the right-hand side, assigning the left-hand side the v alue only after all right-hand sides ar e evaluated. 8.7 Clocks

Answer 352

A clocking scheme in which all state changes occur on a clock edge.

Answer 353

The appr oach used t o determine when data ar e valid and stable r elativ e to the clock.

Answer 354

A memor y element.

Answer 355

A memor y system that emplo ys clocks and wher e data signals ar e read only when the clock indicates that the signal v alues ar e stable. Register le Register le: A state element that consists of a set of r egisters that can be r ead and written b y supplying a r egister number t o be accessed. 8.8 Memor y elements: Flip-ops, latches, and r egisters Flip-op Flip-op: A memor y element for which output is equal t o the v alue of the st ored state inside the element and for which the internal state is changed only on a clock edge.

Answer 356

A memor y element in which the output is equal t o the v alue of the st ored state inside the element and the state is changed whene ver the appr opriate inputs change and the clock is asser ted. D ip-op D ip-op: A ip-op with on data input that st ores the v alue of that input signal in the internal memor y when the clock edge occurs.

Answer 357

The minimum time that the input t o a memor y device must be v alid befor e the clock edge.

Answer 358

The minimum time during which the input must be v alid after the clock edge. 8.9 Memor y elements: SRAMs and DRAMs

Answer 359

A memor y wher e data is st ored statically (as in ip-ops) rather than dynamically (as in DRAM). SRAMs ar e faster than DRAMs, but less dense and mor e expensiv e per bit.

Answer 360

A memor y wher e data is st ored statically (as in ip-ops) rather than dynamically (as in DRAM). SRAMs ar e faster than DRAMs, but less dense and mor e expensiv e per bit.

Answer 361

A code that enables the detection of an err or in data, but not the pr ecise location and, hence, corr ection of the err or. 8.10 Finite-state machines

Answer 362

A sequential logic function consisting of a set of inputs and outputs, a next- state function that maps the curr ent state and the inputs t o a new state, and an output function that maps the curr ent state and possibly the inputs t o a set of asser ted outputs.

Answer 363

A combinational function that, giv en the inputs and the curr ent state, determines the next state of a nite-state machine. 8.11 Timing methodologies

Answer 364

The diff erence in absolute time between the times when two state elements see a clock edge. level-sensitiv e clocking

Answer 365

A timing methodology in which state changes occur at either high or low clock le vels but ar e not instantaneous as such changes ar e in edge-trigger ed designs.

Answer 366

A situation that occurs if a signal is sampled when it is not stable for the r equir ed setup and hold times, possibly causing the sampled v alue t o fall in the indeterminate r egion between a high and low v alue.

Answer 367

A situation in which a ip-op enters a metastable state and wher e some logic blocks r eading the output of the ip-op see a 0 while others see a 1.

Answer 368

The time r equir ed for an input t o a ip-op t o propagate t o the outputs of the ip-op. 8.12 Field pr ogrammable de vices

Answer 369

An integr ated cir cuit containing combinational logic, and possibly memor y devices, that ar e congur able b y the end user .

Answer 370

An integr ated cir cuit containing combinational logic, and possibly memor y devices, that ar e congur able b y the end user .

Answer 371

An integr ated cir cuit containing combinational logic whose function is congur ed b y the end user .

Answer 372

An integr ated cir cuit containing combinational logic whose function is congur ed b y the end user .

Answer 373

A congur able integr ated cir cuit containing both combinational logic blocks and ip-ops.

Answer 374

A congur able integr ated cir cuit containing both combinational logic blocks and ip-ops.

Answer 375

Pr ogrammable logic de vice, usually containing either a single P AL or PL A.

Answer 376

Pr ogrammable logic de vice, usually containing either a single P AL or PL A.

Answer 377

Contains a pr ogrammable and-plane followed b y a x ed or-plane.

Answer 378

Contains a pr ogrammable and-plane followed b y a x ed or-plane.

Answer 379

A structur e in an integr ated cir cuit that when pr ogrammed mak es a permanent connection between two wir es.

Answer 380

In a eld pr ogrammable de vice, the name giv en to the cells because the y consist of a small amount of logic and RAM.

Answer 381

In a eld pr ogrammable de vice, the name giv en to the cells because the y consist of a small amount of logic and RAM. 9. Appendix B 9.1 Introduction

Answer 382

A pr ocessor optimiz ed for 2D and 3D gr aphics, video, visual computing, and displa y.

Answer 383

A pr ocessor optimiz ed for 2D and 3D gr aphics, video, visual computing, and displa y.

Answer 384

A mix of gr aphics pr ocessing and computing that lets y ou visually inter act with computed objects via gr aphics, images, and video.

Answer 385

A system combining diff erent pr ocessor types. A PC is a heter ogeneous CPU-GPU system.

Answer 386

A set of function and data structur e denitions pr oviding an inter face t o a libr ary of functions.

Answer 387

A set of function and data structur e denitions pr oviding an inter face t o a libr ary of functions.

Answer 388

Using a GPU for computing via a par allel pr ogramming language and API.

Answer 389

Using a GPU for gener al-purpose computation via a tr aditional gr aphics API and gr aphics pipeline.

Answer 390

A scalable par allel pr ogramming model and language based on C/C++. It is a par allel programming platform for GPUs and multicor e CPUs. 9.2 GPU system ar chitectur es

Answer 391

A standar d system I/O inter connect that uses point-t o-point links. Links ha ve a congur able number of lanes and bandwidth.

Answer 392

A standar d system I/O inter connect that uses point-t o-point links. Links ha ve a congur able number of lanes and bandwidth. Unied memor y architectur e Unied memor y architectur e (UM A): A system ar chitectur e in which the CPU and GPU shar e a common system memor y. UMA Unied memor y architectur e (UM A): A system ar chitectur e in which the CPU and GPU shar e a common system memor y.

Answer 393

An extended v ersion of the original PCI I/O bus, which pr ovided up t o eight times the bandwidth of the original PCI bus t o a single car d slot. Its primar y purpose was t o connect graphics subsystems int o PC systems. 9.3 Programming GPUs

Answer 394

An open-standar d graphics API.

Answer 395

A gr aphics API dened b y Micr osoft and par tners.

Answer 396

A 1D , 2D, or 3D arr ay that suppor ts sampled and lter ed lookups with interpolated coor dinates.

Answer 397

A pr ogram that oper ates on gr aphics data such as a v ertex or a pix el fragment.

Answer 398

A gr aphics r endering language, usually ha ving a dataow or str eaming programming model.

Answer 399

A pr ogram or function for one thr ead, designed t o be ex ecuted b y many thr eads.

Answer 400

A set of concurr ent thr eads that ex ecute the same thr ead pr ogram and ma y cooper ate t o compute a r esult.

Answer 401

A set of thr ead blocks that ex ecute the same k ernel pr ogram.

Answer 402

Thr eads wait at a synchr onization barrier until all thr eads in the thr ead block arriv e at the barrier .

Answer 403

A memor y read, modify , write oper ation sequence that completes without any inter vening access.

Answer 404

Per-thr ead local memor y priv ate t o the thr ead.

Answer 405

Per-block memor y shar ed b y all thr eads of the block.

Answer 406

Per-application memor y shar ed b y all thr eads.

Answer 407

A style of par allel pr ogramming model in which all thr eads execute the same pr ogram. SPMD thr eads typically coor dinate with barrier synchr onization.

Answer 408

A style of par allel pr ogramming model in which all thr eads execute the same pr ogram. SPMD thr eads typically coor dinate with barrier synchr onization. 9.4 Multithr eaded multipr ocessor ar chitectur e

Answer 409

A pr ocessor ar chitectur e that applies one instruction t o multiple independent thr eads in par allel.

Answer 410

The set of par allel thr eads that ex ecute the same instruction t ogether in a SIM T architectur e.

Answer 411

A set of concurr ent thr eads that ex ecutes the same thr ead program and ma y cooper ate t o compute a r esult. A GPU C TA implements a CUD A thr ead block. 9.6 Floating point arithmetic

Answer 412

A 16-bit binar y oating-point format, with 1 sign bit, 5-bit exponent, 10-bit fr action, and an implied integer bit.

Answer 413

A single oating-point instruction that per forms a compound oper ation: multiplication followed b y addition.

Answer 414

A har dwar e unit that computes special functions and interpoles planar attributes.

Answer 415

A Latin phr ase multum in par vo, or much in a small space. A MIP-map contains precalculated images of diff erent r esolutions, used t o incr ease r endering speed and r educe artifacts.

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