1.1 Structure & Function Of Processor

Question 1

Arithmetic Logic Unit (ALU)

Answer 1

• Completes all arithmetical & logical operations
• Arithmetical operations = mathematical operations (e.g addition/subtraction on fixed/floating point numbers
• Logical operations = boolean logic operations (AND, OR, NOT, XOR)

Question 2

Control Unit

Answer 2

• Component which directs the operations of the CPU & has the following jobs:
• Controlling & coordinating the activities of the CPU
• Managing flow of data between CPU & other devices
• Accepting next instruction
• Decoding instructions
• Storing resulting data back in memory

Question 3

Registers

Answer 3

• Small memory cells that operate at a very high speed
• Used to temporarily store data
• Is where all arithmetic, logical & shift operations occur
• Program Counter (PC): Holds address of the next instruction to be executed
• Accumulator (ACC): Stores results from calculations
• Memory Address Register (MAR): Holds address of location that is to be read from or written to
• Memory Data Register (MDR): Temporarily stores data that has been read/ data that needs to be written.
• Current Instruction Register (CIR): Holds the current instruction being executed, divided up into operand & opcode

Question 4

Buses

Answer 4

Buses: Set of parallel wires which connect two or more components inside the CPU
- Width of bus = No. of parallel wires bus has. Width proportional to the no. of bits that can be transferred (8, 16, 32, 64 wires wide)

Data Bus: Bi-directional bus, bits carried in both directions.
- Used for transporting data & instructions between components

Address Bus: Transmits memory addresses specifying where data is sent to or retrieved from
- Width of the address bus proportional to the no. of
addressable memory locations.

Control Bus: Bi-directional,* transmits control signals between internal & external components*
- Coordinates use of the address & data buses &
provides status information between system components.

Control signals include:
- Bus request: shows a device is requesting use of the data bus
- Bus grant: shows that CPU has granted access to the data bus
- Memory write: data written into addressed location using this bus
- Memory read: data read from specific location to be placed onto the data bus
- Interrupt request: shows that a device is requesting access to CPU
- Clock: used to synchronise operations

Question 5

Assembly Language

Answer 5

• Uses mnemonics to represent instructions (E.g ADD = addition
• Simplified way of representing machine code
• Instruction divided into operand & opcode in CIR
• Operand: contains the data/ address of the data upon which the operation is to be performed
• Opcode: specifies the type of instruction to
  be executed

Question 6

Pipelining

Answer 6

• The process of completing the FDE cycles of 3 separate instructions simultaneously, holding appropriate data in a buffer in close proximity to CPU until it’s required
• While 1 instruction is being executed, another can be decoded & another fetched
• Pipelining aims to reduce amount of the CPU which is kept idle
• Instruction Pipelining: Separating out the instruction into fetching, decoding, & executing
• Arithmetic Pipelining: Breaking down arithmetic operations & overlapping them as they are performed.

Question 7

FDE Cycle & Registers

Answer 7

FDE Cycle: Sequence of operations that are completed in order to execute an instruction
Fetch:
- Address from the PC is copied to the MAR
- Instruction held at that address is copied to MDR by the data bus
- Simultaneously, the contents of the PC are incremented
- The value held in the MDR is copied to the CIR
Decode:
- The contents of CIR are split into operand and opcode
Execute :
- The decoded instruction is executed

Question 8

Factors affecting CPU performance

Answer 8

Clock Speed: Determined by the system clock. The time taken for one clock cycle to complete

No. of Cores: Core is an independent processor that is able to run its own fetch-execute cycle
- Multiple cores can complete more than one fetch-execute cycle
- Not all programs are able to utilise multiple cores
efficiently

Amount & Type of Cache Memory: Cache memory is CPU’s onboard memory
- Instructions fetched from main memory are
copied to the cache, so if required again, they can be accessed quicker
- As cache fills up, unused instructions are replaced

Question 9

Computer Architecture

Answer 9

Von Neumann Architecture:
- Basic components: Single control unit, ALU, registers, & memory units
- Utilizes shared memory and shared data bus for both data & instructions
- Built on the stored program concept
- Cheaper to develop, programs size can be optimised

Harvard Architecture:
- Physically separates memories for instructions & data
- Commonly used in embedded processors
- Useful when memories have different characteristics (e.g., read-only instructions, read-write data)
- Optimizes memory cell & bus sizes based on specific needs
- Allows larger word size for instructions by designing larger instruction memory
- Quicker execution, memories can be different sizes

Question 10

Contemporary Processing

Answer 10

• Contemporary processors use a combination of Harvard & Von Neumann architecture
• Von Neumann is used when working with data & instructions in main memory, but uses Harvard architecture to divide the cache into instruction cache and data cache