CAQA6e_ILP

Question 1

Approach used in server and desktop processors and not used as extensively in PMP processes.

Answer 1

Hardware-based dynamic approaches

Question 2

When exploiting instruction-level parallelism, goal is to ___________.

Answer 2

maximize CPI

Question 3

Pipeline CPI = ?

Answer 3

Ideal Pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls

Question 4

What is the typical size of basic block in parallelism?

Answer 4

3-6 instructions

Question 5

What are the challenges of data dependency?

Answer 5

• Cannot execute simultaneously
• Data Hazard

Question 6

This determines if dependence is detected and if it causes a stall

Answer 6

Pipeline organization

Question 7

What does data dependence conveys?

Answer 7

1. Possibility of a hazard
2. Order in which results must be calculated
3. Upper bound on exploitable instruction level parallelism

Question 8

This dependence is when two instructions use the same name but no flow of information.

Answer 8

Name dependence

Question 9

Not a true data dependence but is a problem when reordering instructions.

Answer 9

Name dependence

Question 10

This dependence is when instruction j writes a register or memory location that instruction i reads

Answer 10

Antidependence

Question 11

What must be preserved for antidependence?

Answer 11

Initial ordering

Question 12

This dependence is when instruction i and j write the same register or memory location

Answer 12

Output dependence

Question 13

What must be preserved for output dependence?

Answer 13

Ordering

Question 14

To resolve name dependencies, what must be used?

Answer 14

Register renaming techniques

Question 15

What are the data hazards?

Answer 15

RAW, WAW, WAR

Question 16

This dependence is the ordering of instruction i with respect to a branch instruction

Answer 16

Control Dependence

Question 17

Instruction control dependent on branch cannot be moved before the branch so that its execution is _______________________.

Answer 17

No longer controlled by the branch

Question 18

This separates dependent instruction from the source instruction by the pipeline latency of the source instruction.

Answer 18

Pipeline scheduling

Question 19

This goals to make k copies of the loop body.

Answer 19

Strip Mining

Question 20

For each branch this predicts taken or not taken.

Answer 20

Basic 2 bit predictor

Question 21

If the prediction is wrong two consecutive times, ______.

Answer 21

change prediction

Question 22

Multiple 2 bit predictors for each branch where one for each possible combination of outcomes of preceding n branches.

Answer 22

Correlating predictor

Question 23

Combines correlating predictor with local predictor.

Answer 23

Tournament Predictor

Question 24

Need to have predictor for each branch and history.

Answer 24

Tagged Hybrid Predictors

Question 25

What is the solution for Tagged Hybrid Predictors creating a huge tables?

Answer 25

Using hash tables whose hash value is based on branch address and branch history.

Question 26

Longer histories may lead to increased _______________, so use _________________.

Answer 26

chance of hash collision. multiple tables with increasingly shorter histories.

Question 27

Rearranges order of instructions to reduce stalls while maintaining data flow.

Answer 27

Dynamic Scheduling

Question 28

Advantages of Dynamic Scheduling

Answer 28

Compiler doesn't need to have knowledge of microarchitecture Handles cases where dependencies are unknown at compile time

Question 29

Disadvantage of Dynamic Scheduling

Answer 29

Substantial increase in hardware complexity Complicates exceptions

Question 30

What does dynamic scheduling implies?

Answer 30

out-of-order execution and completion

Question 31

Introduces register renaming in hardware, minimizing WAW ad WAR hazards.

Answer 31

Tomasulo's Approach

Question 32

Register renaming is provided by __________

Answer 32

reservation station (RS)

Question 33

Execute instructions along predicted execution paths but only commit the results if prediction was correct.

Answer 33

Hardware-based speculation

Question 34

Allowing an instruction to update the register file when instruction is no longer speculative

Answer 34

Instruction commit

Question 35

Need an additional piece of hardware to prevent any irrevocable action until an instruction commits.

Answer 35

Hardware-Based Speculation

Question 36

Holds the result of instruction between completion and commit

Answer 36

Reorder buffer

Question 37

When a mispredicted branches head of ROB, ___________.

Answer 37

discard all entries/ clear ROB

Question 38

These are not recognized until it is ready to commit

Answer 38

Reorder Buffer

Question 39

To achieve CPI < 1, need to ______________.

Answer 39

complete multiple instructions per clock

Question 40

Solutions to achieve multiple instructions per clock

Answer 40

- Statically scheduled superscalar processors - VLIW processors - Dynamically scheduled superscalar processes

Question 41

This packages multiple operations into one instruction

Answer 41

VLIW Processors

Question 42

Examples of VLIW processor?

Answer 42

- One integer instruction (or branch) - Two independent floating-point operations - Two independent memory references

Question 43

Disadvantages of VLIW?

Answer 43

- Statistically finding parallelism - Code Size - No Hazard detection hardware - Binary code compatibility

Question 44

What is the bottleneck in dynamically scheduled superscalars?

Answer 44

Issue logic

Question 45

How to simplify RS allocation?

Answer 45

the number of instructions of a given class can be issued in a "bundle"

Question 46

Adding target instruction into buffer to deal with longer decoding time required by larger buffer

Answer 46

Branch folding

Question 47

Causes the buffer to potentially forget about the return address from previous calls?

Answer 47

unconditional branches coming from multiple sites

Question 48

This creates return address buffer organized as a stack

Answer 48

Return Address Predictor

Question 49

Design monolithic unit that performs branch prediction and instruction prefetch, and instruction memory access and buffering.

Answer 49

Integrated Instruction Fetch Unit

Question 50

Deals with crossing cache lines

Answer 50

Instruction memory access and buffering