CAQA_Memory

Question 1

This ensures that nearly all references can be found in smaller memories.

Answer 1

Temporal and spatial locality

Question 2

This gives the allusion of a large, fast memory being presented to the processor

Answer 2

Temporal and Spatial Locality

Question 3

In a memory hierarchy diagram, the _________ are put at the top while the ______ are put at the bottom

Answer 3

faster and smaller, slower and larger

Question 4

Why is the memory hierarchy design crucial in recent multi-core processors?

Answer 4

CPU speed increases much faster memory speed, leading to the memory wall. Caches are needed to close this gap.

Question 5

What does CPUs need to cope with its huge bandwidth demand?

Answer 5

multi-port caches
per-core L1/L2 caches
shared L3 cache

Question 6

High-end microprocessors have _____ on chip cache.

Answer 6

> 10 MB

Question 7

When a word/data is not found in the cache, a __________ occurs.

Answer 7

miss

Question 8

What does the cache do when a miss occurs?

Answer 8

fetch from lower level in hierarchy that may be another cache or memory. Fetching other words within the block taking advantage of spatial locality

Question 9

n-way = __________

Answer 9

n-blocks per set

Question 10

If one block per set, the cache is

Answer 10

direct-mapped (1-way)

Question 11

If the cache is 1 way but with all blocks inside it, its associativity is

Answer 11

fully associative

Question 12

Immediately update lower levels of hierarchy

Answer 12

Write-through

Question 13

Only update lower levels of hierarchy when an updated block is replaced

Answer 13

Write-back

Question 14

Writing strategies use ___________ to make writes asynchronous.

Answer 14

write buffer

Question 15

Fraction of cache access that result in a miss

Answer 15

Miss rate

Question 16

cause of a miss: first reference to a block

Answer 16

Compulsory

Question 17

cause of miss that blocks discarded and later retrieved

Answer 17

capacity

Question 18

cause of miss: program makes repeated references to multiple addresses from different blocks that map to the same location in the cache

Answer 18

conflict

Question 19

Average memory access time =

Answer 19

Hit time + Miss rate X Miss Penalty

Question 20

misses per instruction =

Answer 20

miss rate X memory accesses/instruction

Question 21

To reduce performance impact of misses

Answer 21

speculative and multithreaded processors may execute other instructions during miss

Question 22

Reduces compulsory misses and Increases capacity and conflict misses, increases miss penalty

Answer 22

Larger block size

Question 23

Increases hit time, increases power consumption

Answer 23

Larger total cache capacity to reduce miss rate

Question 24

Reduces conflict misses and increases hit time, power consumption

Answer 24

Higher associativity

Question 25

Reduces overall memory access time

Answer 25

Higher number of cache levels

Question 26

Reduces miss penalty

Answer 26

Giving priority to read misses over writes

Question 27

Reduces hit time

Answer 27

Avoiding address translation in cache indexing

Question 28

Time between read request and when desired word arrives

Answer 28

Access time

Question 29

Minimum time between unrelated requests to memory

Answer 29

Cycle time

Question 30

Has low latency, use for cache

Answer 30

SRAM

Question 31

Chips into many banks for high bandwidth, use for main memory

Answer 31

Organize DRAM

Question 32

Requires low power to retain bit and 6 transistors/bit

Answer 32

SRAM

Question 33

Must be re-written after being read and must also be periodically refreshed

Answer 33

DRAM

Question 34

In DRAM, upper half of address is

Answer 34

row access strobe (RAS)

Question 35

In DRAM, lower half of address is

Answer 35

column access strobe (CAS)

Question 36

Some optimizations in memory capacity and speed to keep up with processors.

Answer 36

Multiple accesses to same row Synchronous DRAM Wider interfaces Double data rate (DDR) Multiple banks on each DRAM device

Question 37

DDR with lower power (2.5V -> 1.8 V) and clock rates (266 -> 400 MHz)

Answer 37

DDR2

Question 38

DDR with 1.5 V power and 800 MHz clock rate

Answer 38

DDR3

Question 39

DDR with 1-1.2 V power and 1333 MHz clock rate

Answer 39

DDR4

Question 40

Graphics memory based on DDR3

Answer 40

GDDR5

Question 41

Has lower voltage and lower power mode (ignores clock, continues refresh)

Answer 41

SDRAMs

Question 42

Achieve 2-5 X bandwidth per DRAM vs DDR3 and has wider interfaces and higher clock rate

Answer 42

Graphics Memory

Question 43

DRAM stacked vertically with very high bandwidth and used in GPUs and HPC

Answer 43

High Bandwidth Memory (HBM)

Question 44

Non-volatile that is slower than DRAM but faster than disk. It has two types (NAND and NOR)

Answer 44

Flash Memory

Question 45

Must be erased in blocks before being overwritten and can use as little as zero power.

Answer 45

NAND Flash Memory

Question 46

NAND Flash Memory is limited to _____________- number of cycles

Answer 46

100,00

Question 47

Memory is susceptible to __________.

Answer 47

cosmic rays/ soft errors

Question 48

Soft errors are fixed by _____

Answer 48

ECC

Question 49

Hard Errors are permanent errors that are fixed by

Answer 49

replacing it by spare rows

Question 50

a RAID-like error recovery technique

Answer 50

Chipkill

Question 51

To improve hit time, predict the _____ to pre-set mux

Answer 51

way

Question 52

To improve bandwidth

Answer 52

Pipelined caches

Question 53

To support simultaneous access

Answer 53

Multibanked Caches

Question 54

Allow hits while misses are outstanding

Answer 54

Nonblocking caches

Question 55

Request missed word from memory first and send it to the processor as soon as it arrives

Answer 55

Critical word first

Question 56

Request words in normal order and send missed work to the processor as soon as it arrives

Answer 56

Early restart

Question 57

Swaps nested loops to access memory in sequential order

Answer 57

Loop interchange

Question 58

Improves locality of accesses

Answer 58

Blocking

Question 59

Fetch two blocks on miss (include next sequential block)

Answer 59

Hardware Prefetching

Question 60

Insert prefetch instructions before data is needed

Answer 60

Compiler prefetching

Question 61

HBM as a cache where each SDRAM row is a block index and contains set of tags and 29 segments. Hit requires a CAS.

Answer 61

L-H

Question 62

HBM as cache that molds tag and data together and use direct mapped

Answer 62

Alloy cache

Question 63

Keeps processes in their own memory space

Answer 63

Virtual Memory

Question 64

Provide user mode and supervisor mode Protect certain aspects of CPU state Provide mechanisms for switching between user mode and supervisor mode Provide mechanisms to limit memory accesses Provide TLB to translate addresses

Answer 64

Role of architecture

Question 65

Supports isolation and security. Sharing a computer among many unrelated users Enabled by raw speed of processors, making the overhead more acceptable

Answer 65

Virtual Machine