switches

Question 1

Q1. Bootstrap-cap sizing
Scenario: drive a high-side N-ch MOSFET, Qg = 30 nC, Vgs = 10 V, allow 5 % droop, fs = 150 kHz.

Answer 1

Step 1 Charge needed per cycle
Qtot = Qg + 20 % margin = 36 nC

Step 2 Allowed droop
ΔV = 0.05 × 10 V = 0.5 V

Step 3 Minimum Cboot
Cboot ≥ Qtot / ΔV = 36 nC / 0.5 V = 72 nC/V → 72 nF

Step 4 Pick standard & derate
Use 0.1 µF, 25 V X7R (≈ 2× margin)

Step 5 diode & resistor
Fast-recovery 100 V, 1 A diode; 5 Ω gate resistor to damp ringing

Question 2

Q2. Miller-plateau sketch & EMI link

Answer 2

Flat occurs at Vgs = Vth + Id / gm ≈ 3 V + 30 A / 100 S = 3.3 V

Step 2 Label intervals
t1: Vgs to Vth (charging Cgs)
t2: Miller flat (charging Qgd)
t3: remainder to 10 V

Step 3 dV/dt control
Qgd ≈ 10 nC → Igate = Qgd / t2
If t2 = 100 ns → Igate = 0.1 A → choose Rg = (Vdrv – Vplat) / Igate ≈ (12 – 3.3) / 0.1 = 87 Ω

Step 4 EMI trade-off
Longer t2 ⇒ lower dV/dt ⇒ less 30 MHz-200 MHz noise, but higher switching loss ⇒ pick Rg = 22 Ω as compromise (t2 ≈ 40 ns)

Question 3

Miller Plateau four lines

Answer 3

Vplat = Vth + Id / gm
Igate = Qgd / t2
Rg ≈ (Vdrv – Vplat) / Igate
dV/dt = Vbus / t2

Question 4

Shoot-through dead-time trade-off

Answer 4

Half-bridge: 38 V bus, IPP65R045C7 both FETs, fs = 150 kHz

Step 1 Dead-time goal
Body-diode conduction time tdead = 50 ns (min) to 200 ns (max)

Step 2 Diode loss during tdead
Pdiode = Vf · Iload · tdead · fs
Vf = 0.9 V, Iload = 10 A, tdead = 100 ns
P = 0.9 × 10 × 100 n × 150 k = 0.135 W

Step 3 Gate-driver setting
Driver ADuM4121: DT pin resistor 22 k → 100 ns (datasheet curve)
Verify no overlap at 125 °C: measure both gates with 1 GHz scope, ensure < 5 ns overlap

Step 4 EMI vs. loss
Longer dead-time → lower shoot-through current but higher diode loss & reverse-recovery spike ⇒ choose 100 ns as sweet spot