Why interface?
It is easy to end up with systems in which many signals are passed between two blocks. SystemVerilog provides an Interface construct, which offers a new paradigm for modelling large and complex design. The interface construct allows signals to be collected together even though they are moving in different directions
How are modules grouped together?
Instantion, long-winded process?
Instantiation problems?
What does an interface allow you to do?
A module may have more than one interface
Syntax for interface declaration:
Master and Slaves?
The interface sBus?
How are the ports defined on bus?
Overall bus script?
Overall interface design?
It is possible to define the modport in the definition of the module.
master module
It is possible to define the modport in the definition of the module. The master module will use the port configuration from masterPorts defined by modport in the interface. This configuration is accessed with “.” followed by the modport configuration.
It is possible to define the modport in the definition of the module.
Slave module
Slave and master with top modules
Interfacing key details