The basic design of a microprocessors is based on the following architectures
von Neumann architecture
Harvard architecture
Von Neumann Structure?
Advantages of Von Neumann?
- Single memory
- Data and instructions store in the same memory
- Single bus for data and instructions
- Memory and devices controlled by CPU
Disadvantages of Von Neumann?
- One bus is a bottleneck
- Data and instructions can be overwritten by an error in the program
Harvard architecture?
Advantages of Harvard architecture?
- Two memories
- Data and instructions are stored in separate memories
- Two busses to access data and memory separately
- No conflict when using data and instructions
Disadvantages of Harvard architecture?
- More complex control than von Neumann
- Production is more expensive (more busses and complex control)
- Free space in data memory can’t be used for instructions and vice versa
What are stored program computers?
von Neumann and Harvard architectures are stored-program computers, where the program to be executed is stored in and access from the memory.
Earlier computers such as ENIAC employed the program-controlled model, where the programming process was based on connecting wires and configuring switches.
The stored program concept?
The concept of stored-program computer was introduced by John von Neumann in 1947
Main components of a computer?
The main components of a bus?
Example of a bus in system verilog?
The main components of memory?
Example of memory in system verilog?
The main components of the CPU?
A generic microprocessor overview?
Advantages of the generic microprocessor layout?
Our generic CPU example uses a Harvard architecture to keep the data and program memory separate.
This means that we don’t have to manage the issue of the same bus handling everything.
The stages of the fetch-execute cycle in practice?
- Get the instruction from memory
- Decode the instruction
- Decide what to do and do it (getting any data along the way)
- Deal with the resulting data
- Increment the program counter to get the location for the next instruction
FEC: Stage 1?
Stage 1: The PC contains the address of the memory location that has the next instruction that has to be fetched.
Suppose the PC initialised to 0, then PC = 0.
FEC Stage 2?
Stage 2: The address sent through the instruction bus is used to fetch the instruction from the program memory.
FEC Stage 3?
Stage 3: Increment the program counter to fetch the next instruction.
This means that PC = PC + 1
FEC Stage 4?
The execute stage is dependant on the following?
It could be
- Get Data from memory
- Carry out an ALU function
- Store data in a register
- Store data in memory
FEC: Stage 5?
Stage 5: Execute the instruction
-
1 Introduction to FPGA technology6
-
2 Gate Level, Hierarchy and Simulation28
-
3 The Module data types and operators55
-
4 Behavioural descriptions and combinational logic25
-
5 Sequential circuit descriptions26
-
6 Counters16
-
7 State Machines(NOT ASSESSED)11
-
8 Conversion and factoring state machines(NOT ASSESSED)0
-
9 Microprocessors program counter25
-
10 Microprocessors register file11
-
11 Arithmetic Logic Unit (ALU)33
-
12 MIPS and High RISC microprocessors30
-
13 Addition and subtraction33
-
14 Multiplication Methods15
-
15 Fixed and Floating-Point arithmetic23
-
16 Pipelining15
-
17 Memory(NOT ASSESSED)23
-
18 Addressing Modes(NOT ASSESSED)13
-
19 VGA controller(NOT ASSESSED)0
-
20 Slow, fast clocks and memory(NOT ASSESSED)2
-
21 Interfaces(NOT ASSESSED)19
-
22 FPGAs and Cryptography(NOT ASSESSED)0
-
23 FPGAs and Machine Learning(NOT ASSESSED)0
-
Example questions45
