What is polling?
Job maintained by the CPU with relation to I/O.
- Ask devices if operation is pending
- Initiates the processing
- transmittion of data
What is interruptions?
whenever a device requires attention, instead of waiting for the CPU to ask for that, the device is going to notify the CPU. The CPU will stop its normal execution and help the device.
In addition, there’s an array in memory of the interruption routine. That is, for each interrupt there’s a specific behaviour.
What is the difference between control line, address line and data line
- Control line - determines the direction of data flow, and when each device can access the bus
- Data line - conveys bits from one device to another.
- Address line - determine the location of the source or destination of the data.
What is the purpose of each instruction/register
Address decoder:
- Identify whether it is an I/O device(FFFFF000-FFFFFFFF)
- Identify the location of the I/O device(11-3)
- <3> = 1
- Data register - an instruction to print.
- <3>=0
- Status register - an instruction for status of operation.
CPU data register(data bus)
- data<31> - holds the status given by the printer. operation is done
- data<7…0> - holds the character to be moved to the printer
- Read(status)*
- Used by the CPU to know whether the read instruction has been sent to the printer, so it can continue its work.
- Write(data)*
- Used by the CPU to know whether the write instruction has been sent to the printer, so it can continue its work.
- D flip flop*
- Used to hold the character until write instruction is sent.
- when is sent, data shifts from flip flop to printer
- Used to hold status value recieved from the printer.
- enabled when printer has done its work
Simultaneously
- when an instruction to write a character is sent, both the printer is started and the status is set to 0. Only when the printer finishes its work, the status is set to 1.
On device:
what is the job of the status register and output register?
which bits of these registers is used?
- Output register holds the character it gets from CPU. last 8 bits <7…0>
- Status register is set to 1 when job is completed. first 1 bit. <31>
Analyse each step
- If the interrupt request and interrupt enable are set on device, ireq is set.
- If ireq is set and IE is set(Interrupt enable on CPU), we stop normal execution and handle the interrupt in the following way:
- Save on IPC the content of the PC register
- set iack = 1 - tells the device it can send info.
- II register saves information about the interrupt.
- Set IE = 0 - disable CPU interrupts
- we need to treat this case
- set PC = 20@0 # Ivect<7..0> #4@0
- start device software(driver)
- iack = 0
- we got the needed information from driver, we can close the stream.
What are the basic steps which occur in each device software?
- Save used registers on some array
- Stop ie(device level)
- load device control to register
- set off ie bit
- store at device
- Save interrupt data(because we want to be able to handle more interrupts - that is, we need IPC and II registers)
- Enable interrupts(CPU level)
- Load device input and do the specific thing you need to do
- Store the changes on device output
- put send request at control
- Load device control
- Set <31> = 1
- Store control on device
- Stop CPU interrupts(because we want to finish interrupt)
- because we need to enable the device interrupt, but not allowing it to start a new interrupt before this one is ended.
- Enable device interrupts
- restore interrupt vectors.
- restore registers.
Solve and name important points from this question
- Block addressing starts at address 0! not - 8.
- Address changes when we use 2-way direct method. The order of bits changes
- Address size = 1 Byte. Word size = 4 Bytes.
- The sum of bits in address should represent an address. That is, if RAM holds 2^32 addresses, the sum of bits in the address should be summed to 32.
Explain the concept of write allocate, write-back and reread
- Write-allocate - on miss - read block from memory(Memory-Cache) to cache and update(CPU-Cache)*
- Memory->Cache + Cache->CPU
- write-back - on switch, if the switched block is dirty - shift it from Cache to Memory and read block from Memory to cache and then shift from cache to CPU*
- Cache->Memory + Memory->Cache + Cache->Cache
