Goal of Memory Interleaving
To increase memory read or write rates by servicing multiple requests simultaneously using independent memory banks.
SDRAM (Synchronous DRAM)
DRAM that exchanges data with the processor synchronized to an external clock signal and is much faster than traditional DRAM.
DDR SDRAM Transfer Rate
Achieves a double data rate by transferring data on both the rising and falling edges of the clock pulse.
Low-Order Interleaving Addressing
Lower-order bits of the address determine the bank/module, distributing sequential addresses across different banks.
Memory Read Operation Cycle
The memory receives the address, enables the read signal, and eventually provides the data bits to the system bus.
M-bit data word, K check bits, condition for error correction
The code must satisfy the condition: $2^K \ge M + K + 1
Location of Parity Bits in Hamming Code
Parity bits are placed at bit positions that are powers of 2 (position 1, 2, 4, 8, etc.).
General ECC Code Capability (SEC-DED)
Single Error Correction (SEC) and Double Error Detection (DED).
Hard Error in Memory
A permanent physical defect in a memory cell that causes it to be permanently stuck at a 0 or a 1.
Soft Error in Memory
A random, non-destructive event that alters the state of a single memory cell without causing permanent damage (e.g., alpha particle disruption).
Advantage of Core Memory over Early Semiconductor Memory
Core memory was non-volatile, retaining data when power was off, unlike early volatile semiconductor RAM.
Memory Write Operation
The address is placed on the address bus, the data is placed on the data bus, and the write control signal is enabled.
Purpose of the Control Lines
Used to select the memory device, specify read/write direction, and indicate the timing of data availability.
Memory Module with 12 Address Lines and 16 Data Lines
Capacity is $2^{12} \times 16 \text{ bits} = 4,096 \times 2 \text{ bytes} = 8 \text{ KB}$ (since $16 \text{ bits} = 2 \text{ bytes}$).
The term ‘Core’ in Core Magnetic Memory
Refers to tiny magnetic rings that store one binary bit based on their magnetic polarity.
