1
Q
asserted signal
A
A signal that is (logically) true, or 1
2
Q
deasserted signal
A
A signal that is (logically) false, or 0
3
Q
combinatorial logic
A
- A logic system whose blocks do not contain memory
- the output of a combinational block depends only on the current input
4
Q
sequential logic
A
A group of logic elements that contain memory and hence whose value depends on the input as well as the current contents of the memory
5
Q
Digital electronics operate with only two voltage levels of interest
A
- a high voltage and a low voltage
- All other voltage values are temporary and occur while transitioning between the values
6
Q
state
A
- output of a combinational block depends only on the current input
- this can depend on inputs and/or memory
7
Q
OR operator, boolean algebra
A
- represented as +
- ex. A + B is A OR B
8
Q
AND operator, boolean algebra
A
- represented as *
- ex. A * B is A AND B
9
Q
NOT, operator, boolean algebra
A
- represented as ̄ (line over variable)
10
Q
gates
A
- A device that implements basic logic functions, such as AND or OR
- can be represented in circuit diagrams
11
Q
NOR gate
A
An inverted OR gate
12
Q
NAND gate
A
An inverted AND gate
13
Q
decoder
A
- A logic block that has an n-bit input and 2^n outputs, where only one output is asserted for each input combination
- outputs are usually numbered (for input i result is output i)
14
Q
encoder
A
performs the inverse function of a decoder, taking 2^n inputs and producing an n-bit output
15
Q
multiplexor/selector
A
- its output is one of the inputs that is selected by a control value
- so inputs are input values and a control value(s)
- ex. inputs A and B with selector S is C = (A * !S) + (B * S)
16
Q
selector/control value
A
The control signal that is used to select one of the input values of a multiplexor as the output of the multiplexor
17
Q
how many selectors are needed given n inputs
A
log_2_ n
(log base 2 of n)
18
Q
example of architecture of a multiplexor
A
- decoder that generates n signals, each indicating a different input value
- array of n AND gates, each combining one of the inputs with a signal from the decoder
- single large OR gate that incorporates the outputs of the AND gates
19
Q
two level logic
A
- writing a logic function with exclusively AND or OR gates
- can be done for any function
20
Q
sum of products (SOP)
A
form of logical representation that employs a logical sum (OR) of products (terms joined using the AND operator)
21
Q
product of sums (POS)
A
form of logical representation that employs a logical product (AND) of sums (terms joined using the OR operator)
22
Q
how to write SOP equation
A
- find all cases where output is true
- individually multiply inputs together
- add up every true case
23
Q
Programmable Logic Array (PLA)
A
- corresponds with SOP
- a set of inputs and corresponding input complements (which can be implemented with a set of inverters), and two stages of logic
- first stage is an array of AND gates that form a set of product terms (can consist of any of the inputs or their complements)
- second stage is an array of OR gates, each of which forms a logical sum of any number of the product terms
24
Q
product terms/minterms
A
- a set of logic inputs joined by conjunction (AND operations)
- the product terms form the first logic stage of the programmable logic array (PLA)
25
Read-only memory (ROM)
- memory whose contents are designated at creation time, after which the contents can only be read -- used as structured logic to implement a set of logic functions by using the terms in the logic functions as address inputs and the outputs as bits in each word of the memory
26
Programmable ROM (PROM)
A form of read-only memory that can be programmed when a designer knows its contents
27
don't cares
- situations where don't care what the output is
- important because they make it easier to optimize the implementation of a logic function
28
bus
- a collection of data lines that is treated together as a single logical signal
- also, a shared collection of lines with multiple sources and uses
29
inverted input
any logic gate where at least one of its input signals is passed through a NOT gate (inverter) before reaching the main logic gate
30
PLA and how they represent truth tables
- each entry where the output is true has a product term, there will be a corresponding row in the PLA
- output corresponds to a potential row of OR gates in the second stage
31
architecture of a ROM
- # of addressable entries in the ROM determines the number of address lines
- if ROM contains 2^m addressable entries, called the height, then there are m input lines
- # of bits in each addressable entry = # output bits and is sometimes called the width of the ROM
- total number of bits in the ROM is equal to the height times the width (sometimes called the shape)
32
ROM vs. PLA
- ROM is fully decoded, PLA is partially decoded (ROM always has more entries)
- ROMs grow exponentially, PLAs slower w more input (more efficient)
33
using truth tables to create ROMs
- n functions with m inputs, we need a ROM with m address lines (and 2^m entries), with each entry being n bits wide
- entries in the input portion of the truth table represent the addresses of the entries in the ROM, while the contents of the output portion of the truth table constitute the contents of the ROM
34
output don't cares
- arise when we don't care about the value of an output for some input combination
- appear as X's in the output portion of a truth table
35
input don't cares
- arise when an output depends on only some of the inputs
- appear as X's in the input portion of a truth table
36
arrays of logic elements
- when there's a bunch of bits to perform the same operation on, easier to make them a collection
- can represent simply by showing that a given operation will happen to an entire collection of inputs
37
bus representation/facts
- represented with a thicker line
- most are 64 bits wide
38
topology
the arrangement of elements in a computer network or mathematical concepts that describe the structure of data and systems
39
HW and SW: When is input accepted and what input is acceptable
SW: accepts input when commanded and as specified
HW: Combinatorial HW continuously accepts voltage inputs
Voltage inputs are acceptable when their values are within the ranges of the two bands for logic 0 and 1
40
HW and SW: behavior
SW: translate from source to machine code, load memory, link w/libraries, call from operating system
Very complicated
HW: turn on the power supply
41
HW and SW: function
SW: decided at any time, basically limitless
HW: logic gate, fixed in advance
- Limited to a few choices
- Execution time measured in intervals of very small seconds for today’s gates
42
HW and SW: output
SW: various forms, formatted, any symbols, to any output device
HW: one of two voltages on one wire
43
edge-triggered clocking
A clocking scheme in which all state changes occur on a clock edge
44
clocking methodology
The approach used to determine when data are valid and stable relative to the clock (when to change state basically)
45
synchronous system
A memory system that employs clocks and where data signals are read only when the clock indicates that the signal values are stable (not changing unless inputs change)
46
register file
state element that consists of a set of registers that can be read and written by supplying a register number to be accessed
47
fast carry schemes
- trying to speed up addition by determining the carry in to the high-order bits sooner
- equation expands for higher bits reflected in the cost of the hardware for fast carry
48
generate (gi)
- used in carry lookahead adders
- gi = ai * bi
49
propogate (pi)
- used in carry lookahead adders
- pi = ai + bi
50
carry-lookahead adder
- a fast digital adder that reduces the delay of carry propagation by calculating carry bits simultaneously
- relies on some level of abstraction
51
clocks
- needed in sequential logic to decide when an element that contains state should be updated
- free-running signal with a fixed cycle time
52
state element
A memory element
53
how clock edges work with memory
acts as a sampling signal, causing the value of the data input to a state element to be sampled and stored in the state element (a clock edge)
CS250
flashcards
Decks in class (17)
# Cards
