1
Q
fields
A
- specific portions of a binary instruction (w several bits) that contain different pieces of information
- like a unit of data in machine code
2
Q
instruction format
A
- A form of representation of an instruction composed of fields of binary numbers
- all LEGv8 instructions are 32 bits long
3
Q
machine language
A
Binary representation of instructions used for communication within a computer system
4
Q
hexadecimal
A
- Numbers in base 16
- can convert back and forth with base 2 binary since 16 = 2^4
- numbers 10-15 are a-f
5
Q
opcode
A
- The field that denotes the operation and format of an instruction
- ex. ADD becoming a field
- usually appear at beginning of instruction
- each operation has its own number so computer knows how to format instruction
6
Q
how register are converted into binary fields
A
- saves the binary value of the register number in a field
- saves 0 if empty/unused
7
Q
ex. how ADD X3, X2, X1 goes into fields
A
- ADD goes in register 1, X1 in register 2, X2 in register 4, X3 in register 5
- register 3 is unused
8
Q
how hexadecimal labels correspond with binary
A
- 0000 to 1001 (0 to 9) are labeled as 0 to 9 in hexadecimal
- 1010 to 1111 is labeled as a-f
- notation 0xnnnn is common for hexadecimal
9
Q
Rm
A
- The second register source operand
- X1 in ADD X3, X2, X1
10
Q
shamt
A
- the shift about in a field
- represents the bit shift amount in bit shifts left/right
11
Q
Rn
A
- The first register source operand
- ex. X2 in ADD X3, X2, X1
12
Q
Rd
A
- The register destination operand
- It gets the result of the operation
- ex. X3 in ADD X3, X2, X1
13
Q
destination register
A
a register that receives the result of an operation
14
Q
what to do when an instruction needs longer fields?
A
- change the formatting for a given instruction
- ex. R-format (for registers) versus D-format (for loads and stores)
15
Q
d-format field order
A
- used for loads and stores
opcode, address, op2, Rn, Rt - Rt indicates data source, opcode is operation, Rn is first register source
16
Q
i-format field order
A
- used for immediate adding (ADDI, SUBI)
- opcode, immediate, Rn, Rd
17
Q
immediate value
A
- a value that is directly encoded within CPU instruction rather than being fetched from register/memory
- basically a constant
18
Q
shifts
A
a logical operation that moves all the bits in a doubleword to the left or right, filling the emptied bits with 0s
19
Q
LSL (logical shift left)
A
- shifts all the bits in a doubleword to the left by a given amount
- ex. LSL X11, X19, #4 shifts X19 by 4 bits, stores it in X11
20
Q
LSR (logical shift right)
A
- shifts all the bits in a doubleword to the right by a given amount
- ex. LSR X11, X19, #4 shifts X19 by 4 bits, stores it in X11
21
Q
AND
A
- A logical bit- by-bit operation with two operands that calculates a 1 only if there is a 1 in both operands
- in logic operations bit is only 1 if both are 1
22
Q
mask
A
- a bitwise operation used to selectively modify, extract, or test bits within a data value
- ex. using AND just to see all 1s
23
Q
OR
A
A logical bit-by-bit operation with two operands that calculates a 1 if there is a 1 in either operand
24
Q
NOT
A
A logical bit-by-bit operation with one operand that inverts the bits; that is, it replaces every 1 with a 0, and every 0 with a 1
25
what multipying/dividing by 2 looks like in binary
shifting left or right respectively
26
EOR
A logical bit-by-bit operation with two operands that calculates the exclusive OR of the two operands. That is, it calculates a 1 only if the values are different in the two operands (can't be both true or both false)
27
CBZ register, L1
- This instruction means go to the statement labeled L1 if the value in register equals zero
- The mnemonic CBZ stands for compare and branch if zero
28
CBNZ register, L1
- means go to the statement labeled L1 if the value in register does not equal zero
- The mnemonic CBNZ stands for compare and branch if not zero
29
conditional branch
An instruction that tests a value and that allows for a subsequent transfer of control to a new address in the program based on the outcome of the test
30
basic block
- A sequence of instructions without branches (except possibly at the end) and without branch targets or branch labels (except possibly at the beginning)
- ex. executing a loop
31
branch address table/branch table
a table of addresses of alternative instruction sequences
32
B.cond
- a conditional branch instruction that can be used for any of the sign instructions
- ex. B.EQ, B.GT (greater than), B.LE (less than or equal to)
33
SUBS
- Performs the subtraction, stores the result, and also updates the NZCV flags
- These flags are essential for conditional branching.
34
XZR
- a special 64-bit register that serves as a zero register
- This means it is hard-wired to always read the value 0
35
SUBIS
- performs a subtract immediate and set flags operation
- ex. SUBIS, XZR, X3, #4 subtracts 4 from X3 and sets flags accordingly
36
ORR
- ex. ORR X1, X2, X3
- bitwise operator OR
- X1 = X2 | X3
37
ORRI
- ex. ORRI X1, X2, #20
- bitwise operator or with a constant
- X1 = X2 | 20
38
AND
- AND, X1, X2, X3
- bitwise operator AND
- X1 = X2 & X3
39
ANDI
- ANDI, X1, X2, #20
- bitwise operator and with a constant
- X1 = X2 & 20
40
EORI
- EORI X1, X2, #20
- bitwise operator exclusive or with a constant
- X1 = X2 ^ 20
41
kilobyte (abbreviation and value)
KB, 10^3
42
megabyte (abbreviation and value)
MB, 10^6
43
gigabyte (abbreviation and value)
GB, 10^9
44
terabyte (abbreviation and value)
TB, 10^12
45
kibibyte (abbreviation and value)
KiB, 2^10
46
mebibyte (abbreviation and value)
MiB, 2^20
47
gibibyte (abbreviation and value)
GiB, 2^30
48
tebibyte (abbreviation and value)
TiB, 2^30
49
length of LEGv8 doubleword
- 64 bits (8 bytes)
- why PLAs or adders will be 64 bits wide to account for all possible inputs coming in
50
length of all LEGv8 instructions
- 32 bits
- made that way for consistent formatting
51
a register is made up of....
- multiple flip-flops
- each flip flop stores a bit so when they're grouped together they make a bit string that can represent a register number
CS250
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