1
Q
pipelining
A
- An implementation technique in which multiple instructions are overlapped in execution, much like an assembly line
- is nearly universal today
2
Q
structural hazard
A
- Don’t have enough hardware to do processing needed for single instruction
- ex. two instructions trying to use the same ALU at the same time
- doesn’t happen much because LEGv8 designed with pipelining in mind
3
Q
data hazard/pipeline data hazard
A
When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available
Example:
ADD X19, X0, X1
SUB X2, X19, X3
4
Q
forwarding/bypassing
A
- A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory
- basically adding hardware to retrieve missing item ASAP
- valid only if the destination stage is later in time than the source stage
5
Q
load-use data hazard
A
A specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction
6
Q
pipeline stall/bubble
A
- a stall initiated in order to resolve a hazard
- explicitly stated in instructions because code always need to be told what to do
7
Q
control hazard/branch hazard
A
- arising from the need to make a decision based on the results of one instruction while others are executing
- when the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed
8
Q
branch prediction
A
- a method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome
- often used because stalling takes time
- usually assume branching is untaken, just stall when it is taken
9
Q
NOP
A
- No-operation Instruction
- allows hardware to waste time without destroying program
- fills time in the pipeline and is crafted to have no effect on program behavior
10
Q
ISA
A
- Instruction Set Architecture
- the abstract model of a computer that defines the complete set of instructions a processor can understand/execute
- interface between computer software and hardware
11
Q
latency
A
- the number of stages in a pipeline or the number of stages between two instructions during execution
- ex. amount of time it takes to start and finish laundry
12
Q
throughput
A
- the number of instructions completed per unit of time
- with pipelining, the number of stages completed in a clock cycle
13
Q
classic RISC pipeline
A
Divides fetch-execute cycle into 5 steps:
- IM fetches current instruction from iM
- ID/IF decodes MI and fetches its operands from registers
- EX performs ALU operation
- MEM accesses (writes/reads) data to memory if it is a LDUR/STUR
- WB writes ALU or LOAD result to destination register
14
Q
ILP
A
- Instruction Level Parallelism
- ability of processor to execute multiple instructions (MIs) at the same time
- finds independent instructions and runs them concurrently
15
Q
CPI
A
- Clocks Per Instruction (CPI)
- CPI is a metic widely used to assess processor pipeline circuit designs
- Lower CPI is better
16
Q
what it means when pipelines are said to be transparent
A
- every language contains no information about the presence or absence of a pipeline design for the processor circuit
- nice that you don’t need to know, but compiler does
17
Q
things adding a NOP should NOT do (3 things)
A
- change what a program returns
- cause a program to throw an exception, prevent a program from throwing an exception it normally would
- cause a program to crash, prevent a program from crashing that would have
18
Q
instruction fetch
A
- grabbing current machine instruction (MI) from instruction memory
- the first step in any datapath for instruction execution
19
Q
stages
A
- a step in a linear sequence of operations where data is processed, like a station on an assembly line
- ideally performs part of an instruction/stage at same time as others
20
Q
what pipeline improves and what it doesn’t improve
A
- pipelining improves throughput (# instructions/unit of time)
- pipelining does NOT improve latency (amount of time an entire instruction takes)
21
Q
5 steps to execute a basic pipeline
A
- Fetch instruction from memory.
- Read registers and decode the instruction.
- Execute the operation or calculate an address.
- Access an operand in data memory (if necessary)
- Write the result into a register (if necessary)
22
Q
what limits were we can start to overlap instructions?
A
- limited by the slowest resource
- ex. doing three LDURs, instruction fetch is slowest so must do that first before starting on another LDUR
23
Q
why x86 can’t use pipelining
A
- in LEGv8, all instructions are same length (32 bits), so makes it easy to determine stages
- x86 instructions vary from 1-15 bits, so hard to pipeline
24
Q
hazards
A
situations in pipelining when the next instruction cannot execute in the following clock cycle
25
the five pieces a datapath gets separated into for pipelining
IF: Instruction fetch
ID: Instruction decode and register file read
EX: Execution or address calculation
MEM: Data memory access
WB: Write back
26
ABI
27
IM (instruction memory)
- the part of the computer's memory that stores the program's instructions, which are then fetched, decoded, and executed by the CPU
- in instruction steps/pipelining, the first stage of every instruction
28
Reg (register)
- is where an instruction is read from and then written to after it gets operated on
- one of the stages (2nd and 5th) in pipelining
29
DM (data memory)
- used for storing and retrieving data for operands, acting as a workspace for the processor to save and load values
- the 4th stage in pipelining
30
stale data
- in pipelining, when data hasn't been updated to its current value but is needed for another instruction
- hardware needs to be able to detect this (multiplexor)
31
how do we get correct bits to right place in pipelining?
- with multiplexors and a forwarding unit
- help direct control flow to execute forwarding
32
forwarding unit
- detects hazards and controls MUXes to choose the “normal path” or the forwarding path
- doesn't forward data itself, sets control lines on MUXes to select the right data source
33
what ID/EX, EX/MEM, MEM/WB do in the datapath
- called pipeline latches
- buffers between stages that save the necessary data so that each pipeline stage can work independently on a different instruction at the same time
34
what do we have to do to use pipelining at the software level?
- literally nothing
- get performance benefit without having to think about it
CS250
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