1
Q
arithmetic logic unit (ALU)
A
- the brawn of the computer
- the device that performs the arithmetic operations like addition and subtraction or logical operations like AND and OR
2
Q
1 bit ALU
A
- A and B input in AND and OR gates
- multiplexor on the right then selects a AND b or a OR b, depending on whether the value of operation is 0 or 1
- aka multiplexor chooses which operation to carry out
3
Q
64 bit ALU
A
- created by connecting adjacent “black boxes” of 1 bit ALUs
- the adder created by directly linking the carries of 1-bit adders is called a ripple carry adder
4
Q
1 bit adder
A
ex. full adder that has 3 inputs, 2 outputs (2 inputs and carryIn, sum and carryOut)
5
Q
CarryOut
A
- single that indicates the overflow resulting from an arithmetic operation like addition
- part of adder’s output,
6
Q
CarryIn
A
- single binary input signal to adder that represents the carry bit from a less significant digit position
- basically carrying the one to the next part of addition (5+7, carry the 1, is a carry in for the 10s place)
7
Q
adder
A
- performs binary addition where its output (sum and carry) depends on only its current inputs (not on previous memory)
- made up of a two bit input and one bit output
8
Q
static random access memory (SRAM)
A
- memory where data is stored statically (as in flip-flops) rather than dynamically (as in DRAM)
- SRAMs are faster than DRAMs, but less dense and more expensive per bit
9
Q
how adders do subtraction
A
- adds the negative version of the operand
- shortcut for negating a two’s complement number is to invert each bit and then add 1
- can be done with 2:1 multiplexor that chooses between b and b!
10
Q
ripple carry adder
A
adder created by directly linking the carries of 1-bit adders
11
Q
DeMorgan’s Theorem
A
NOT(a OR B) = NOT a AND NOT b
!(A + B) = !A * !B
12
Q
instructions
A
words of a computer’s language
13
Q
instruction set
A
- the vocabulary of commands understood by a given architecture
- usually quite similar between computers
14
Q
why are instruction sets so similar?
A
- all computers are constructed from hardware technologies based on similar underlying principles
- there are a few basic operations that all computers must provide
15
Q
stored program concept
A
The idea that instructions and data of many types can be stored in memory as numbers and thus be easy to change, leading to the stored-program computer
16
Q
LEGv8 instruction to add two numbers
A
- variables a, b, and c
- notation ADD a, b, c, adds b+c and stores it in a
- rigid notation, must do one operation with three variables
17
Q
comments/statements in LEGv8
A
- only one instruction per line
- comments are started with // and always terminate at the end of a line
18
Q
LEGv8 instruction to subtract two numbers
A
- variables a, b, c
- notation SUB a, b, c subtracts b-c and stores it in a
- rigid notation, must do one operation with three variables
19
Q
why only three operands?
A
- keeps hardware simple
- illustrates the first of three underlying principles of hardware design: Simplicity favors regularity
20
Q
how a basic addition statement is computed w hardware (4 steps)
A
- compiler translate code to assembly language
- assembly instruction operates on two source operands and places the result in one destination operand
- one code addition statement is compiled into one assembly language statement
- add instruction puts result in register of variable
21
Q
LEGv8 operands: 32 registers
A
- ex. X0 … X30, XZR
- goes up to X30 max and XZR is always 0
- fast locations for data, which in LEGv8 must be in registers to perform arithmetic
22
Q
LEGv8 operands: 2^62 memory words
A
- Memory[0], Memory [8], …., Memory[18,446,744,073,709,551,608]
- Accessed only by data transfer instructions
- LEGv8 uses byte addresses, so sequential double word addresses differ by 8
- holds data structures, arrays, and spilled registers.
23
Q
word
A
A natural unit of access in a computer, usually a group of 32 bits
24
Q
double word
A
- natural unit of access in a computer, usually a group of 64 bits
- corresponds to the size of a register in the LEGv8 architecture
25
registers
- limited # of special locations used in hardware design that temporarily hold data (ex. operands of arithmetic instructions HAVE TO BE registers)
- visible to the programmer when the computer is completed
26
why is there usually a limit of 32 registers?
- second of our three underlying design principles, smaller is faster
- large number of registers take longer because farther traveling for signals
27
registers and clock signals
With more registers, the clock signal requires more time to reach every register, so the clock frequency must be slower
28
data transfer instruction
- A command that moves data between memory and registers
- ex. moving results of arithmetic to memory
29
address
- A value used to represent the location of a specific data element within a memory array
- memory is just one giant array
30
load/load register
- the data transfer instruction that copies data from memory to a register
- format is the name of the operation followed by the register to be loaded, then register and a constant used to access memory
- LDUR X1, [X2, #16]
31
base address
the starting address of an array in memory in an LDUR instruction
32
base register
a register that holds an array's base address
33
offset
a constant value added to a base address to locate a particular array element
34
LDUR
- an assembly language instruction that stands for load register
- ex. LDUR X1, [X2, #64]
35
alignment restrictions
- A requirement that data be aligned in memory on natural boundaries
- ex. base words are multiples of 4, base doublewords are multiples of 8
36
doubleword addresses in memory
- addresses are multiples of 8 (because 8 bytes in a doubleword)
- each doubleword has its 8 bytes with addresses 0, 1, 2, 3, 4, 5, 6, 7
37
big-endian or little-endian with memory
computers either use the address of the leftmost or "big end" byte as the doubleword address versus those that use the rightmost or "little end" byte
38
store
- copies register data into memory
- format is name of operation, followed by the register to be stored, then the base register, and finally the offset to select the array element
- STUR X1, [X2, #16]
39
what happens when more variables than registers
compiler keeps most frequently used variables in registers and puts rest in memory via loads/stores
40
which is faster, access through registers or memory?
registers, because fewer of them so less time to access and higher throughput
41
ADDI
takes three operands and immediately adds a constant
- ex. ADDI X19, X23, #5 will compute X23 + 5 and save it in X19
42
binary digit/binary bit
- One of the two numbers in base 2, 0 or 1, that are the components of information
- in any number base, the value of ith digit d is (d x base^i) where i starts at 0 and increases from right to left, base is 2, and d is a 0 or 1
43
least significant bit
- The rightmost bit in an LEGv8 doubleword
- this is bit 0 in LEGv8
44
most significant bit
- The leftmost bit in an LEGv8 doubleword
- this is bit 63 in LEGv8
45
overflow
- when the number that is the result of operations cannot be represented by these rightmost hardware bits
- up to computer to decide how to handle this
46
sign and magnitude representation
- a signed number representation where a single bit is used to represent the sign, and the remaining bits represent the magnitude (number)
- because of all the issues w it it was quickly abandoned
47
two's complement
- signed number representation where a leading 0 indicates a positive number and a leading 1 indicates a negative number
- complement of a value is obtained by complementing each bit (0 → 1 or 1 → 0), and then adding one to the result
- makes it easy for hardware to spot them because check most significant bit
48
signextension
- the process of increasing the bit length of a binary number while preserving its signed value
- ex. positive numbers adding 0's to the left
49
one's complement
notation where positive numbers are represented in their standard form and negative numbers are represented by flipping all the bits of the corresponding positive number
50
biased notation
A notation that represents the most negative value by 00 … 000two and the most positive value by 11 … 11two, with 0 typically having the value 10 … 00two, thereby biasing the number such that the number plus the bias has a non-negative representation.
51
signed number
a number representation that can store both positive and negative values
52
unsigned number
a whole number than can only represent zero or positive values
53
why are numbers kept in base 2
Numbers are kept in computer hardware as a series of high and low electronic signals and so considered base 2 numbers
54
how to calculate the largest number that can be represented by n bits
2^n - 1
55
In a two's complement representation, the magnitude of the largest negative value is one greater than the magnitude of the largest positive number
- Zero is one of the positive values, leaving one less value available for the other positives
- ex. -128 is a possible value for 8-bits
56
when does overflow happen with two's complement?
when the numbers' sign bits match, but yield a sum with a different sign bit
57
load byte (LDURB)
- treats the byte as an unsigned number and thus zero-extend it, writing to the register
- used to expand a binary number while preserving its value
- ex. LDURB X10, [X2, #0]
58
load byte signed (LDURSB)
- works with signed integers
- not used very often
- used to expand a binary number while preserving its value
59
shortcut is a quick way to negate a two's complement binary number
invert every 0 to 1 and every 1 to 0, then add one to the result
60
sign extension
- shortcut that converts a binary number represented in n bits to a number represented with more than n bits
- take the most significant bit from the smaller quantity—the sign bit—and replicate it to fill the new bits of the larger quantity
61
the output from any memory element depends on
the inputs and on the value that has been stored inside the memory elemen
62
memory element
a fundamental digital circuit/component designed to store information, often a single data bit, by having multiple stable states
63
unclocked memory element
a memory element that does not have clock input (not used in textbook)
64
flip-flop
- A memory element for which output is equal to the value of the stored state inside the element
- the internal state is changed only on a clock edge
65
latch
- A memory element in which the output = the value of the stored state inside the element
- the state is changed whenever the appropriate inputs change and the clock is asserted
66
d flip-flop
- A flip-flop that stores the value of its data (D) input at the time of an active clock edge
- 2 inputs (value to store D, clock signal C) 2 outputs (value of internal state and complement Q, Q!)
67
setup time
The minimum time that the input to a memory device must be valid before the clock edge
68
hold time
The minimum time during which the input must be valid after the clock edge
69
flip-flops vs. latches
- latch is level sensitive, responds when clock/enable is at a level (high or low), NOT transitions
- in flip-flop, the state is changed only on a clock edge, so TRANSITIONS
70
register file
- consists of a set of registers that can be read and written by supplying a register number to be accessed
- can be implemented with a decoder for each read or write port and an array of registers built from D flip-flops
71
Static random access memory (SRAM)
- A memory where data is stored statically (as in flip-flops) rather than dynamically (as in DRAM)
- faster than DRAMs, but less dense and more expensive per bit
72
dynamic RAM (DRAM)
- the value kept in a cell is stored as a charge in a capacitor
- single transistor is then used to access this stored charge, either to read the value or to overwrite the charge stored there
- much denser and cheaper per bit
- memory cannot be kept forever and has to be refreshed
73
Error detection code
A code that enables the detection of an error in data, but not the precise location and, hence, correction of the error
74
bit line
how large memories are implemented with a shared output line which multiple memory cells in the memory array can assert
75
how to refresh a DRAM
read its contents and write it back
76
parity code
- the number of 1s in a word is counted; the word has odd parity if the number of 1s is odd and even otherwise
- When a word is written into memory, the parity bit is also written (1 for odd, 0 for even).
- Then, when the word is read out, the parity bit is read and checked
- If the parity of the memory word and the stored parity bit do not match, an error has occurred
77
finite-state machine
- a logic function consisting of inputs/outputs, a next-state function that maps the current state and the inputs to a new state, and an output function that maps the current state and possibly the inputs to a set of asserted outputs
- used to represent sequential logic
- if there are n bits of storage, there are 2^n states
78
next-state function
combinational function that, given the inputs and the current state, determines the next state of a finite-state machine
79
what does it mean to have a synchronous state machine
- the state changes together with the clock cycle, and a new state is computed once every clock
- thus, state elements are only updated on clock edge
- how ones are that are in the textbook
80
Moore machine
- When a finite-state machine is used as a controller, the output function is often restricted to depend on just the current state
- how ones are that we use in the textbook
81
Mealy machine
the output function can depend on both the current state and the current input
82
Lookup table (LUTs)
In a field programmable device, the name given to the cells because they consist of a small amount of logic and RAM
83
field programmable devices (FPD)
An integrated circuit containing combinational logic, and possibly memory devices, that are configurable by the end user
84
STUR
- instruction that acts as a store
- STUR X9, [X22, #8] stores x9 in memory (base plus the constant #)
85
reading is a ____ event, writing is a ____ event
combinatorial, sequential
CS250
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