1
Q
MIPS vs. ARMv8
A
- both have 32 registers, start with opcode in each register, register for 0
- both can only access memory via loads/stores and have 32-bit instructions
- ARMv8 has more instructions than full MIPS instruction set
- MIPS uses comparison instructions/branches for conditional branching ARMv8 uses conditional codes
2
Q
ARMv7 vs. ARMv8
A
- ARMv8 is much more like MIPS than ARMv7
- ARMv8 has more general purpose registers than ARMv7
- only ARMv7 has instructions to load/store multiple instructions with one command and optional divide instruction
3
Q
general purpose register (GPR)
A
A register that can be used for addresses or for data with virtually any instruction
4
Q
x86
A
- drove the PC generation of computers and still dominates the Cloud portion of the post-PC era
- most popular desktop architecture
5
Q
difference with operands in x86 vs. ARMv8/MIPS
A
- x86 uses one operand for the source and destination
- ARMv7, ARMv8 and MIPS allow separate registers for source and destination
- x86 can have an operand in memory, the other ones covered can’t
6
Q
double word vs. word size
A
- double word is 8 bytes (64 bits)
- word is 4 bytes (32 bits)
7
Q
x86 integer operations (four things)
A
- Data movement instructions (move, push, and pop)
- Arithmetic and logic instructions (test, integer, and decimal operations)
- Control flow (unconditional/conditional branches, calls, and returns)
- String instructions (string move and string compare)
8
Q
how to convert a 64 bit operation to 32 bits in ARMv8
A
- registers W0, W1, … are used for 32 bits
ADD X9, X21, X9
can be turned into a 32-bit operation by writing instead
ADD W9, W21, W9
9
Q
unique feature of the ARMv8
A
second register of all arithmetic and logical processing operations has the option of being shifted before being operated on
10
Q
ADDS
A
does the regular add of the registers with the right half of the operands and sets the condition codes
11
Q
ADC
A
adds the values in two operands along with the current value of the carry flag, storing the result in a destination register
12
Q
ASR
A
- is the arithmetic shift right
- divides a signed number by a power of 2 by shifting bits to the right and copying the sign bit to the vacated positions
13
Q
ROR
A
- is the rotate right
- the bits shift off to the right and are inserted on the left
14
Q
MOVN
A
performs a bitwise logical NOT on the source operand before moving the result into the destination register
15
Q
things that can be represented as bits
A
- words
- machine instructions (machine code!)
- integers
- floats
- most finite data
15
Q
how addition works with binary
A
- just like human addition
- add right to left and carries pass to the next digits on the left
16
Q
how subtraction works with binary
A
- negate the correct binary operand
- use two’s complement, negate all bits then add one
- perform addition like you would normally/how binary does it
17
Q
overflow
A
- occurs when result from an operation cannot be represented with the available hardware
- when we subtract a negative number from a positive number and get a negative result or vice versa
- when adding two negatives makes a positive or vice versa
- can determine overflow by leftmost bit
18
Q
arithmetic logic unit (ALU)
A
Hardware that performs addition, subtraction, and usually logical operations such as AND and OR
19
Q
reminder of when overflow is impossible
A
When positive and negative operands are added, because the result’s magnitude will surely be less than the larger of the two operands.
20
Q
how multiplication works with binary
A
- basically just like human multiplication
- start at rightmost digit of multiplier and multiple it with each digit in multiplicand, right to left
- start over with next digit in multiplier but shift result one left
- add up all the products at the end
21
Q
Moore’s law with binary multiplication
A
- Faster multiplications are possible by essentially providing one 64-bit adder for each bit of the multiplier
- use 63 organized adders to perform operations all at once instead of one adder 63 times (pipelining!!)
22
Q
multiplicand
A
- the first operand in a multiplication
- ex. 3 in 3 * 5
23
Q
multiplier
A
- the second operand in a multiplication
- ex. 5 in 3 * 5
24
the amount of bits a multiplication operation takes
- with n bits times m bits
- n + m bits are used for product
- must look out for overflow
25
how multiplication works in hardware (simple implementation)
- Product, ALU and multiplicand are 128 bits wide, multiplier is 64 bits
- when rightmost bit in multiplicand/multiplier is 0, multiplicand shifts left 1 bit, multiplier shifts right
- when it's 1, gets added and written to product register
- repeats 64 times to compute the product
26
why is the multiplicand 128 bits?
because the multiplier is 64 bits and the multiplicand needs to be able to move once for every bit (128 total)
27
how multiplication works in hardware (optimized implementation)
- multiplicand and ALU are 64 bits wide (no multiplier register)
- product register is 128 bits wide
- ALU adds the upper 64-bits of the Product (where multiplier is)
with the 64-bit Multiplicand
- result is stored in upper 64 bits, shifts right 1 bit every iteration
28
dealing with signed numbers in binary multiplication
convert operators to positive and then remember their original signs for result
29
dividend
A number being divided
30
divisor
A number that the dividend is divided by
31
quotient
The primary result of a division; a number that when multiplied by the divisor and added to the remainder produces the dividend
32
remainder
The secondary result of a division; a number that when added to the product of the quotient and the divisor produces the dividend
33
scientific notation
- A notation that puts a single digit to the left of the decimal point multiplied by a power of 10^n
- can show binary in scientific notation ex. 1.0 X 2^-1
- notice base is 2 instead of 10 for binary
34
normalized
A number in floating-point notation that has no 0s to the left of the last real digit
35
fraction
the value, generally between 0 and 1, placed in the fraction register
35
floating point
Computer arithmetic that represents numbers in which the binary point is not fixed
- literally a decimal
36
exponent
in the numerical representation system of floating-point arithmetic, the value that is placed in the exponent field of the register
37
overflow (floating point)
- A situation in which a positive exponent becomes too large to fit in the exponent field
- aka too large to be represented
38
underflow (floating point)
- A situation in which a negative exponent becomes too large to fit in the exponent field
- aka too small to be represented
39
double precision
- A floating-point value represented in a 64-bit doubleword
- allows for bigger/smaller decimals since original float is in 32 bits
- 1 bit for sign, 11 for exponent, rest of that register plus another 32 bit register for fraction
40
exception/interrupt
- an unscheduled event that disrupts program execution
- used to detect overflow
- address of the instruction that overflowed is saved in a register, and the computer jumps to a predefined address to invoke the appropriate routine for that exception
40
single precision
- A floating-point value represented in a 32-bit word
- typical representation for a float
41
interrupt
- An exception that comes from outside of the processor
- Some architectures use the term interrupt for all exceptions
42
NaN
- symbol for the result of invalid operations, such as 0/0 or subtracting infinity from infinity
- purpose of NaNs is to allow programmers to postpone some tests/decisions for later when they are convenient
43
guard
44
round
45
units in the last place (ulp)
46
sticky bit
47
fused multiply add
48
how division works in binary
basically same as regular division
49
how division works in hardware (simple implementation)
- quotient is 64 bits and set to 0, divisor, ALU, and remainder is 128 bits
- subtract divisor from remainder and put it in remainder
- If the Remainder is negative, a 0 is shifted into the least significant bit of the Quotient register, original remainder value is restored
- If the Remainder is positive, then the divisor <= dividend, shifts Quotient left 1 bit and places a 1 in the least significant bit
- shifts the Divisor register 1 bit to the right, repeats 65 times
50
how division works in hardware (optimized implementation)
- remainder register is 128 bits, ALU, quotient, and dividend are 64 bits
- reduces hardware needed to perform the divide operation by combining the Quotient register with the right half of the Remainder
- speedup comes from shifting the operands and the quotient simultaneously with the subtraction
51
how to do signed division
remember the signs of the divisor and dividend and then negate the quotient if the signs disagree
52
signed divide (SDIV)
- divide and treat operands as signed
- ex. SDIV X1, X2, X3 divides X2 by X3 and saves it in X1
53
divide unsigned (UDIV)
- divide and treat operands as unsigned
- ex. UDIV X1, X2, X3 divides X2 by X3 and saves it in X1
54
do multiplication/division hardware support signed division?
- yes, operands are first converted to positive numbers, and then divided using the same division hardware
- change sign after operation if needed
55
do SDIV/UDIV detect overflow and dividing by 0?
no, the software must check the divisor to detect division by 0, as well as check the division operation for overflow
56
can we use multiple ALUs to make division faster like with multiplication?
- no, the sign of subtraction of remainder and dividend is not known beforehand, needed to determine next step
- use prediction to try to make it faster
57
representation of a LEGv8 floating-point number
- 32 bits total
- first bit is sign of float
- 8 bits for exponent, rest for fraction
- in form (-1)^S * F * 2^E
58
IEEE 754 floating-point standard (form for floats)
(-1)^S * (1 + fraction) * 2^E
59
IEEE 754 characteristics
- found in virtually every computer
- instead of interrupting on a divide by 0, software can set the result to a bit pattern representing +∞ or −∞; the largest exponent is reserved for these special symbols
- has symbol for NaN (not a number)
60
biased notation in IEEE 754 (single or double precision)
- used in IEEE 754 with bias being the number subtracted from a normal, unsigned representation to determine the real value
- form (-1)^S + (1 + fraction) + 2^(exp - bias)
- the bias is 127 bits for single precision IEEE 754, 1023 for double precision
61
how to convert a decimal to floating point representation (5 steps)
- ex. -0.75, first represent as a fraction and with base 2, ---> -3 / 2^2
- convert to binary and scientific notation ---> (-11) / 2^2, -1.1 * 2^(-1)
- convert to single precision notation
---> (-1)^1 + (1 + 0.1000) + 2^(126-127)
- gets put into 32 bit register in sign, exponent, fraction part order
- converted to double precision (bias is now 1023 bits) and put in 64 bit register
62
converting binary to decimal floating point
- remember sign is in first bit, 8 bits for exponent, rest are for the fraction part
- convert register sections back to base 10
- plug into single/double precision binary representation (biased notation, go right to left and it's _ * 2^-1, _ * 2^ -2, _ * 2^-3, etc.)
- add/multiply everything out
63
reminder for all floating pointer/decimal calculations
- always represent your numbers as a decimal (even if it's a whole number)
- ex. 26.0
64
floating point addition (4 steps)
- align the two numbers by adjusting the smaller exponent so their scientific notation matches
- add their decimal parts together like normal binary addition
- readjust sum so it's in scientific notation
- if there's overflow/underflow, throw exception/interrupt
- truncate digits according to how many places you can have (usually 4)
65
reminders for floating point addition
- shifting decimal left SHRINKS exponent in binary
- Rounding may require the result to be normalized again
- The "Increment or decrement" and "Shift left or right" hardware normalize the sum
- an ALU determines which
CS250
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