Week 8

Question 1

subword parallelism

Answer 1

• takes advantage of byte- and halfword-sized data by partitioning the adder to perform multiple operations in parallel
• adder can be configured to add sixteen 8-bit operands, 8 16-bit operands, four 32-bit operations, or 2 64-bit operations operands simultaneously in one instruction

Question 2

the ADD instruction with subwords has

Answer 2

• includes support for 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit numbers
• Operands can be integers, but not floating point numbers

Question 3

V0, V2, ….

Answer 3

• 32 128-bit registers (V0, V1,…,V31) and more than 500 machine-language instructions to support subword parallelism
• supports all the subword data types (8-bit, 16-bit, 32-bit, 64-bit, and 128-bit signed/unsigned integers, 32-bit and 64-bit floating point numbers)

Question 4

first two steps for every instruction (always the same)

Answer 4

• Send the program counter (PC) to the memory that contains the code and fetch the instruction from that memory
• Read one or two registers, using fields of the instruction to select the registers to read
• For the LDUR and CBZ instructions, we need to read only one register, but most other instructions require reading two registers

Question 5

what the basic implementation of a LEGv8 subset contains (and what it doesn’t)

Answer 5

• contains datapath, control and memory
• doesn’t contain input or output, since there’s no additional mechanisms that control what happens (and outcome is writing to register, not output)

Question 6

combinatorial element (for LEGv8 data path implementation)

Answer 6

• An operational element, such as an AND gate or an ALU
• elements that operate on data values are all combinational

Question 7

sequential/state element (for LEGv8 data path implementation)

Answer 7

• a memory element, such as a register or a memory that depends on input and contents of internal state/storage
• if computer got plug pulled would lose data unless they were saved somewhere in main memory

Question 8

clocking methodology

Answer 8

• the approach used to determine when data is valid and stable relative to the clock
• defines when signals can be read and when they can be written

Question 9

edge-triggered methodology

Answer 9

• A clocking scheme in which all state changes occur on a clock edge
• for this class everything is positive edge-triggered (changes on rising edge)

Question 10

control signal

Answer 10

• a signal used for multiplexor selection or for directing the operation of a functional unit
• contrasts with a data signal, which contains information that is operated on by a functional unit

Question 11

asserted

Answer 11

The signal is logically high or true (is 1)

Question 12

deasserted

Answer 12

The signal is logically low or false (or 0)

Question 13

datapath element

Answer 13

• unit used to operate on or hold data within a processor
• In LEGv8 implementation, the datapath elements include the instruction and data memories, the register file, the ALU, and adders

Question 14

program counter (PC)

Answer 14

• The register containing the address of the next instruction in the program to be executed
• first step in using any instruction it using PC to load in instruction

Question 15

register file

Answer 15

• the structure that stores the 32 registers
• any register can be read or written by specifying the number of the register in the file
• also contains register state of the computer

Question 16

sign-extend

Answer 16

To increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item

Question 17

branch taken

Answer 17

• A branch where the branch condition is satisfied and the program counter (PC) becomes the branch target
• All unconditional branches are taken branches

Question 18

branch not taken/untaken branch

Answer 18

• A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch

Question 19

datapath

Answer 19

the hardware component of a computer’s central processing unit that performs arithmetic, logical, and data transfer operations

Question 20

clocks and registers are

Answer 20

sequential/state elements

Question 21

ALUs and truth tables are

Answer 21

combinatorial elements

Question 22

rising clock edge refers to the clock changing from

Answer 22

• 0 to 1
• 0 to 1 is “rising” due to changing from a lower value (0) to a higher value (1)

Question 23

how PC is used in a datapath (2 steps)

Answer 23

• After the PC is written with an address on a positive clock edge, a new instruction is read from the instruction memory
• Simultaneously, the next address is calculated, waiting to be written to the PC on the next positive clock edge

Question 24

key things about instructions that write/read in same line

Answer 24

• write/read can happen in the same cycle since they are edge-triggered (have a set order)
• doesn’t have to wait to output values on a rising clock edge
• PC counter increments by 4 bytes

Question 25

branch target address

Answer 25

- the address specified in a branch, which becomes the new program counter (PC) if the branch is take - the branch target is given by the sum of the offset field of the instruction and the address of the branch